Commit 6c7ffa7a authored by Khaled Almahallawy's avatar Khaled Almahallawy Committed by Jani Nikula
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drm/i915/dp: Add TPS4 PHY test pattern support 



Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.

v2: rebase
v3:
  - Enable TPS4 only for supported platforms (Jani)
  - Uppercase in macro names (Jani)
  - Fix indentation (Jani)
  - Use drm_warn instead of WARN
v4: Disable TPS4 pattern on supported platforms only

Bspec: 50482, 50484, 7557
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: default avatarKhaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231213211542.3585105-2-khaled.almahallawy@intel.com
parent 8e1cd40d

drivers/gpu/drm/i915/display/intel_dp.c

+17 −1
Original line number Diff line number Diff line
@@ -4679,6 +4679,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
	struct drm_dp_phy_test_params *data =

			&intel_dp->compliance.test_data.phytest;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	enum pipe pipe = crtc->pipe;

	u32 pattern_val;
@@ -4686,6 +4687,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
	case DP_LINK_QUAL_PATTERN_DISABLE:

		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);

		if (DISPLAY_VER(dev_priv) >= 10)

			intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),

				     DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,

				     DP_TP_CTL_LINK_TRAIN_NORMAL);

		break;

	case DP_LINK_QUAL_PATTERN_D10_2:

		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
@@ -4733,8 +4738,19 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |

			       pattern_val);

		break;

	case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:

		if (DISPLAY_VER(dev_priv) < 10)  {

			drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");

			break;

		}

		drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);

		intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),

			     DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,

			     DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4);

		break;

	default:

		WARN(1, "Invalid Phy Test Pattern\n");

		drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");

	}

}

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -5652,6 +5652,10 @@ enum skl_power_gate { 
#define  DP_TP_CTL_MODE_SST			(0 << 27)

#define  DP_TP_CTL_MODE_MST			(1 << 27)

#define  DP_TP_CTL_FORCE_ACT			(1 << 25)

#define  DP_TP_CTL_TRAIN_PAT4_SEL_MASK		(3 << 19)

#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4A		(0 << 19)

#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4B		(1 << 19)

#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4C		(2 << 19)

#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1 << 18)

#define  DP_TP_CTL_FDI_AUTOTRAIN		(1 << 15)

#define  DP_TP_CTL_LINK_TRAIN_MASK		(7 << 8)