Commit 6f0c228e authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
Browse files

drm/amd/display: Disable seamless boot on 128b/132b encoding 



[why]
preOS will not support display mode programming and link training
for UHBR rates.

[how]
If we detect a sink that's UHBR capable, disable seamless boot

Reviewed-by: default avatarAnthony Koo <anthony.koo@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarSung Joon Kim <sungjoon.kim@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce649bd2

drivers/gpu/drm/amd/display/dc/core/dc.c

+3 −0
Original line number Diff line number Diff line
@@ -1801,6 +1801,9 @@ bool dc_validate_boot_timing(const struct dc *dc, 
		return false;

	}



	if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED)

		return false;



	if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {

		DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");

		return false;