Commit 6f167a36 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2024-02-15' of... 

Merge tag 'drm-intel-gt-next-2024-02-15' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

UAPI Changes:

- Add GuC submission interface version query (Tvrtko Ursulin)

Driver Changes:

Fixes/improvements/new stuff:

- Atomically invalidate userptr on mmu-notifier (Jonathan Cavitt)
- Update handling of MMIO triggered reports (Umesh Nerlige Ramappa)
- Don't make assumptions about intel_wakeref_t type (Jani Nikula)
- Add workaround 14019877138 [xelpg] (Tejas Upadhyay)
- Allow for very slow HuC loading [huc] (John Harrison)
- Flush context destruction worker at suspend [guc] (Alan Previn)
- Close deregister-context race against CT-loss [guc] (Alan Previn)
- Avoid circular locking issue on busyness flush [guc] (John Harrison)
- Use rc6.supported flag from intel_gt for rc6_enable sysfs (Juan Escamilla)
- Reflect the true and current status of rc6_enable (Juan Escamilla)
- Wake GT before sending H2G message [mtl] (Vinay Belgaumkar)
- Restart the heartbeat timer when forcing a pulse (John Harrison)

Future platform enablement:

- Extend driver code of Xe_LPG to Xe_LPG+ [xelpg] (Harish Chegondi)
- Extend some workarounds/tuning to gfx version 12.74 [xelpg] (Matt Roper)

Miscellaneous:

- Reconcile Excess struct member kernel-doc warnings (Randy Dunlap)
- Change wa and EU_PERF_CNTL registers to MCR type [guc] (Shuicheng Lin)
- Add flex arrays to struct i915_syncmap (Erick Archer)
- Increasing the sleep time for live_rc6_manual [selftests] (Anirban Sk)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Zc3iIVsiAwo+bu10@tursulin-desk
parents b13cfb44 eb927f01

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+0 −8
Original line number Diff line number Diff line
@@ -2160,12 +2160,6 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) 


#ifdef CONFIG_MMU_NOTIFIER

	if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) {

		read_lock(&eb->i915->mm.notifier_lock);



		/*

		 * count is always at least 1, otherwise __EXEC_USERPTR_USED

		 * could not have been set

		 */

		for (i = 0; i < count; i++) {

			struct eb_vma *ev = &eb->vma[i];

			struct drm_i915_gem_object *obj = ev->vma->obj;
@@ -2177,8 +2171,6 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) 
			if (err)

				break;

		}



		read_unlock(&eb->i915->mm.notifier_lock);

	}

#endif

drivers/gpu/drm/i915/gem/i915_gem_pm.c

+10 −0
Original line number Diff line number Diff line
@@ -28,6 +28,13 @@ void i915_gem_suspend(struct drm_i915_private *i915) 
	GEM_TRACE("%s\n", dev_name(i915->drm.dev));



	intel_wakeref_auto(&i915->runtime_pm.userfault_wakeref, 0);

	/*

	 * On rare occasions, we've observed the fence completion triggers

	 * free_engines asynchronously via rcu_call. Ensure those are done.

	 * This path is only called on suspend, so it's an acceptable cost.

	 */

	rcu_barrier();



	flush_workqueue(i915->wq);



	/*
@@ -160,6 +167,9 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) 
	 * machine in an unusable condition.

	 */



	/* Like i915_gem_suspend, flush tasks staged from fence triggers */

	rcu_barrier();



	for_each_gt(gt, i915, i)

		intel_gt_suspend_late(gt);

drivers/gpu/drm/i915/gem/i915_gem_userptr.c

+0 −42
Original line number Diff line number Diff line
@@ -42,7 +42,6 @@ 
#include "i915_drv.h"

#include "i915_gem_ioctls.h"

#include "i915_gem_object.h"

#include "i915_gem_userptr.h"

#include "i915_scatterlist.h"



#ifdef CONFIG_MMU_NOTIFIER
@@ -61,36 +60,7 @@ static bool i915_gem_userptr_invalidate(struct mmu_interval_notifier *mni, 
					const struct mmu_notifier_range *range,

					unsigned long cur_seq)

{

	struct drm_i915_gem_object *obj = container_of(mni, struct drm_i915_gem_object, userptr.notifier);

	struct drm_i915_private *i915 = to_i915(obj->base.dev);

	long r;



	if (!mmu_notifier_range_blockable(range))

		return false;



	write_lock(&i915->mm.notifier_lock);



	mmu_interval_set_seq(mni, cur_seq);



	write_unlock(&i915->mm.notifier_lock);



	/*

	 * We don't wait when the process is exiting. This is valid

	 * because the object will be cleaned up anyway.

	 *

	 * This is also temporarily required as a hack, because we

	 * cannot currently force non-consistent batch buffers to preempt

	 * and reschedule by waiting on it, hanging processes on exit.

	 */

	if (current->flags & PF_EXITING)

		return true;



	/* we will unbind on next submission, still have userptr pins */

	r = dma_resv_wait_timeout(obj->base.resv, DMA_RESV_USAGE_BOOKKEEP, false,

				  MAX_SCHEDULE_TIMEOUT);

	if (r <= 0)

		drm_err(&i915->drm, "(%ld) failed to wait for idle\n", r);



	return true;

}
@@ -580,15 +550,3 @@ i915_gem_userptr_ioctl(struct drm_device *dev, 
#endif

}

int i915_gem_init_userptr(struct drm_i915_private *dev_priv)

{

#ifdef CONFIG_MMU_NOTIFIER

	rwlock_init(&dev_priv->mm.notifier_lock);

#endif



	return 0;

}



void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv)

{

}

drivers/gpu/drm/i915/gem/i915_gem_userptr.h

deleted100644 → 0
+0 −14
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2021 Intel Corporation

 */



#ifndef __I915_GEM_USERPTR_H__

#define __I915_GEM_USERPTR_H__



struct drm_i915_private;



int i915_gem_init_userptr(struct drm_i915_private *dev_priv);

void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);



#endif /* __I915_GEM_USERPTR_H__ */

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs) 
static int mtl_dummy_pipe_control(struct i915_request *rq)

{

	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||

	if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||

	    IS_DG2(rq->i915)) {

		u32 *cs;
@@ -822,7 +822,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
		flags |= PIPE_CONTROL_FLUSH_L3;



	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))

		/* dummy PIPE_CONTROL + depth flush */

		cs = gen12_emit_pipe_control(cs, 0,

					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);