Unverified Commit 6f172175 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-visconti', 'clk-imx', 'clk-microchip', 'clk-rockchip' and...

Merge branches 'clk-visconti', 'clk-imx', 'clk-microchip', 'clk-rockchip' and 'clk-qcom' into clk-next

* clk-visconti:
  clk: visconti: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Add VIIF clocks
  dt-bindings: clock: tmpv770x: Remove definition of number of clocks
  clk: visconti: Do not define number of clocks in bindings

* clk-imx:
  clk: imx: add driver for imx8ulp's sim lpav
  dt-bindings: clock: document 8ULP's SIM LPAV
  clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code
  clk: imx: Add some delay before deassert the reset

* clk-microchip:
  reset: mpfs: add non-auxiliary bus probing
  clk: lan966x: remove unused dt-bindings include
  clk: microchip: mpfs: use regmap for clocks
  dt-bindings: clk: microchip: mpfs: remove first reg region

* clk-rockchip:
  clk: rockchip: Add clock and reset driver for RK3506
  dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
  clk: rockchip: Add clock controller for the RV1126B
  dt-bindings: clock, reset: Add support for rv1126b
  clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
  dt-bindings: clock: rk3568: Drop CLK_NR_CLKS define
  clk: rockchip: rk3568: Drop CLK_NR_CLKS usage
  dt-bindings: clock: rk3568: Add SCMI clock ids

* clk-qcom: (48 commits)
  clk: qcom: Mark camcc_sm7150_hws static
  clk: qcom: x1e80100-dispcc: Add USB4 router link resets
  dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
  clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
  dt-bindings: clock: qcom: Add SM8750 video clock controller
  clk: qcom: branch: Extend invert logic for branch2 mem clocks
  clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
  clk: qcom: clk_mem_branch: add enable mask and invert flags
  clk: qcom: mmcc-sdm660: Add missing MDSS reset
  dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset
  clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers
  clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure
  dt-bindings: clock: qcom: Add Kaanapali Global clock controller
  dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali
  clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
  clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops
  clk: qcom: camcc-sm7150: Fix PLL config of PLL2
  clk: qcom: camcc-sm6350: Fix PLL config of PLL2
  clk: qcom: Add NSS clock controller driver for IPQ5424
  ...
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+72 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ULP LPAV System Integration Module (SIM)

maintainers:
  - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

description:
  The i.MX8ULP LPAV subsystem contains a block control module known as
  SIM LPAV, which offers functionalities such as clock gating or reset
  line assertion/de-assertion.

properties:
  compatible:
    const: fsl,imx8ulp-sim-lpav

  reg:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: bus
      - const: core
      - const: plat

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  mux-controller:
    $ref: /schemas/mux/reg-mux.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - mux-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8ulp-clock.h>

    clock-controller@2da50000 {
        compatible = "fsl,imx8ulp-sim-lpav";
        reg = <0x2da50000 0x10000>;
        clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
                 <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
                 <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
        clock-names = "bus", "core", "plat";
        #clock-cells = <1>;
        #reset-cells = <1>;

        mux-controller {
            compatible = "reg-mux";
            #mux-control-cells = <1>;
            mux-reg-masks = <0x8 0x00000200>;
        };
    };
+22 −14
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ properties:
    const: microchip,mpfs-clkcfg

  reg:
    items:
    oneOf:
      - items:
          - description: |
              clock config registers:
              These registers contain enable, reset & divider tables for the, cpu,
@@ -32,6 +33,12 @@ properties:
              mss pll dri registers:
              Block of registers responsible for dynamic reconfiguration of the mss
              pll
        deprecated: true
      - items:
          - description: |
              mss pll dri registers:
              Block of registers responsible for dynamic reconfiguration of the mss
              pll

  clocks:
    maxItems: 1
@@ -69,11 +76,12 @@ examples:
  - |
    #include <dt-bindings/clock/microchip,mpfs-clock.h>
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
            clkcfg: clock-controller@20002000 {
            #address-cells = <1>;
            #size-cells = <1>;

            clkcfg: clock-controller@3E001000 {
                compatible = "microchip,mpfs-clkcfg";
                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
                reg = <0x3E001000 0x1000>;
                clocks = <&ref>;
                #clock-cells = <1>;
        };
+55 −8
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
@@ -12,21 +12,29 @@ maintainers:

description: |
  Qualcomm networking sub system clock control module provides the clocks,
  resets on IPQ9574
  resets on IPQ9574 and IPQ5424

  See also::
  See also:
    include/dt-bindings/clock/qcom,ipq5424-nsscc.h
    include/dt-bindings/clock/qcom,ipq9574-nsscc.h
    include/dt-bindings/reset/qcom,ipq5424-nsscc.h
    include/dt-bindings/reset/qcom,ipq9574-nsscc.h

properties:
  compatible:
    const: qcom,ipq9574-nsscc
    enum:
      - qcom,ipq5424-nsscc
      - qcom,ipq9574-nsscc

  clocks:
    items:
      - description: Board XO source
      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
      - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
          can vary for different IPQ SoCs. For example, it is 1200 MHz on the
          IPQ9574 and 300 MHz on the IPQ5424.
      - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
          rate can vary for different IPQ SoCs. For example, it is 353 MHz
          on the IPQ9574 and 375 MHz on the IPQ5424.
      - description: GCC GPLL0 OUT AUX clock source
      - description: Uniphy0 NSS Rx clock source
      - description: Uniphy0 NSS Tx clock source
@@ -42,8 +50,12 @@ properties:
  clock-names:
    items:
      - const: xo
      - const: nss_1200
      - const: ppe_353
      - enum:
          - nss_1200
          - nss
      - enum:
          - ppe_353
          - ppe
      - const: gpll0_out
      - const: uniphy0_rx
      - const: uniphy0_tx
@@ -60,6 +72,40 @@ required:

allOf:
  - $ref: qcom,gcc.yaml#
  - if:
      properties:
        compatible:
          const: qcom,ipq9574-nsscc
    then:
      properties:
        clock-names:
          items:
            - const: xo
            - const: nss_1200
            - const: ppe_353
            - const: gpll0_out
            - const: uniphy0_rx
            - const: uniphy0_tx
            - const: uniphy1_rx
            - const: uniphy1_tx
            - const: uniphy2_rx
            - const: uniphy2_tx
            - const: bus
    else:
      properties:
        clock-names:
          items:
            - const: xo
            - const: nss
            - const: ppe
            - const: gpll0_out
            - const: uniphy0_rx
            - const: uniphy0_tx
            - const: uniphy1_rx
            - const: uniphy1_tx
            - const: uniphy2_rx
            - const: uniphy2_tx
            - const: bus

unevaluatedProperties: false

@@ -94,5 +140,6 @@ examples:
                    "bus";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #interconnect-cells = <1>;
    };
...
+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties:
  compatible:
    enum:
      - qcom,glymur-rpmh-clk
      - qcom,kaanapali-rpmh-clk
      - qcom,milos-rpmh-clk
      - qcom,qcs615-rpmh-clk
      - qcom,qdu1000-rpmh-clk
+4 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM8450

maintainers:
  - Taniya Das <quic_tdas@quicinc.com>
  - Taniya Das <taniya.das@oss.qualcomm.com>
  - Jagadeesh Kona <quic_jkona@quicinc.com>

description: |
@@ -17,6 +17,7 @@ description: |
  See also:
    include/dt-bindings/clock/qcom,sm8450-videocc.h
    include/dt-bindings/clock/qcom,sm8650-videocc.h
    include/dt-bindings/clock/qcom,sm8750-videocc.h

properties:
  compatible:
@@ -25,6 +26,7 @@ properties:
      - qcom,sm8475-videocc
      - qcom,sm8550-videocc
      - qcom,sm8650-videocc
      - qcom,sm8750-videocc
      - qcom,x1e80100-videocc

  clocks:
@@ -61,6 +63,7 @@ allOf:
            enum:
              - qcom,sm8450-videocc
              - qcom,sm8550-videocc
              - qcom,sm8750-videocc
    then:
      required:
        - required-opps
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