Commit 6fb44438 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Catalin Marinas:
 "A quick summary: perf support for Branch Record Buffer Extensions
  (BRBE), typical PMU hardware updates, small additions to MTE for
  store-only tag checking and exposing non-address bits to signal
  handlers, HAVE_LIVEPATCH enabled on arm64, VMAP_STACK forced on.

  There is also a TLBI optimisation on hardware that does not require
  break-before-make when changing the user PTEs between contiguous and
  non-contiguous.

  More details:

  Perf and PMU updates:

   - Add support for new (v3) Hisilicon SLLC and DDRC PMUs

   - Add support for Arm-NI PMU integrations that share interrupts
     between clock domains within a given instance

   - Allow SPE to be configured with a lower sample period than the
     minimum recommendation advertised by PMSIDR_EL1.Interval

   - Add suppport for Arm's "Branch Record Buffer Extension" (BRBE)

   - Adjust the perf watchdog period according to cpu frequency changes

   - Minor driver fixes and cleanups

  Hardware features:

   - Support for MTE store-only checking (FEAT_MTE_STORE_ONLY)

   - Support for reporting the non-address bits during a synchronous MTE
     tag check fault (FEAT_MTE_TAGGED_FAR)

   - Optimise the TLBI when folding/unfolding contiguous PTEs on
     hardware with FEAT_BBM (break-before-make) level 2 and no TLB
     conflict aborts

  Software features:

   - Enable HAVE_LIVEPATCH after implementing arch_stack_walk_reliable()
     and using the text-poke API for late module relocations

   - Force VMAP_STACK always on and change arm64_efi_rt_init() to use
     arch_alloc_vmap_stack() in order to avoid KASAN false positives

  ACPI:

   - Improve SPCR handling and messaging on systems lacking an SPCR
     table

  Debug:

   - Simplify the debug exception entry path

   - Drop redundant DBG_MDSCR_* macros

  Kselftests:

   - Cleanups and improvements for SME, SVE and FPSIMD tests

  Miscellaneous:

   - Optimise loop to reduce redundant operations in contpte_ptep_get()

   - Remove ISB when resetting POR_EL0 during signal handling

   - Mark the kernel as tainted on SEA and SError panic

   - Remove redundant gcs_free() call"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (93 commits)
  arm64/gcs: task_gcs_el0_enable() should use passed task
  arm64: Kconfig: Keep selects somewhat alphabetically ordered
  arm64: signal: Remove ISB when resetting POR_EL0
  kselftest/arm64: Handle attempts to disable SM on SME only systems
  kselftest/arm64: Fix SVE write data generation for SME only systems
  kselftest/arm64: Test SME on SME only systems in fp-ptrace
  kselftest/arm64: Test FPSIMD format data writes via NT_ARM_SVE in fp-ptrace
  kselftest/arm64: Allow sve-ptrace to run on SME only systems
  arm64/mm: Drop redundant addr increment in set_huge_pte_at()
  kselftest/arm4: Provide local defines for AT_HWCAP3
  arm64: Mark kernel as tainted on SAE and SError panic
  arm64/gcs: Don't call gcs_free() when releasing task_struct
  drivers/perf: hisi: Support PMUs with no interrupt
  drivers/perf: hisi: Relax the event number check of v2 PMUs
  drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver
  drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information
  drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver
  drivers/perf: hisi: Simplify the probe process for each DDRC version
  perf/arm-ni: Support sharing IRQs within an NI instance
  perf/arm-ni: Consolidate CPU affinity handling
  ...
parents 3bb38c52 5b1ae9de

Documentation/arch/arm64/booting.rst

+21 −0
Original line number Diff line number Diff line
@@ -388,6 +388,27 @@ Before jumping into the kernel, the following conditions must be met: 


    - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.



  For CPUs with the Branch Record Buffer Extension (FEAT_BRBE):



  - If EL3 is present:



    - MDCR_EL3.SBRBE (bits 33:32) must be initialised to 0b01 or 0b11.



  - If the kernel is entered at EL1 and EL2 is present:



    - BRBCR_EL2.CC (bit 3) must be initialised to 0b1.

    - BRBCR_EL2.MPRED (bit 4) must be initialised to 0b1.



    - HDFGRTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.

    - HDFGRTR_EL2.nBRBCTL  (bit 60) must be initialised to 0b1.

    - HDFGRTR_EL2.nBRBIDR  (bit 59) must be initialised to 0b1.



    - HDFGWTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.

    - HDFGWTR_EL2.nBRBCTL  (bit 60) must be initialised to 0b1.



    - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.

    - HFGITR_EL2.nBRBINJ  (bit 55) must be initialised to 0b1.



  For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9):



 - If EL3 is present:

Documentation/arch/arm64/elf_hwcaps.rst

+6 −0
Original line number Diff line number Diff line
@@ -435,6 +435,12 @@ HWCAP2_SME_SF8DP4 
HWCAP2_POE

    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.



HWCAP3_MTE_FAR

    Functionality implied by ID_AA64PFR2_EL1.MTEFAR == 0b0001.



HWCAP3_MTE_STORE_ONLY

    Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

Documentation/arch/arm64/tagged-pointers.rst

+6 −5
Original line number Diff line number Diff line
@@ -60,11 +60,12 @@ that signal handlers in applications making use of tags cannot rely 
on the tag information for user virtual addresses being maintained

in these fields unless the flag was set.



Due to architecture limitations, bits 63:60 of the fault address

are not preserved in response to synchronous tag check faults

(SEGV_MTESERR) even if SA_EXPOSE_TAGBITS was set. Applications should

treat the values of these bits as undefined in order to accommodate

future architecture revisions which may preserve the bits.

If FEAT_MTE_TAGGED_FAR (Armv8.9) is supported, bits 63:60 of the fault address

are preserved in response to synchronous tag check faults (SEGV_MTESERR)

otherwise not preserved even if SA_EXPOSE_TAGBITS was set.

Applications should interpret the values of these bits based on

the support for the HWCAP3_MTE_FAR. If the support is not present,

the values of these bits should be considered as undefined otherwise valid.



For signals raised in response to watchpoint debug exceptions, the

tag information will be preserved regardless of the SA_EXPOSE_TAGBITS

arch/arm64/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -232,6 +232,7 @@ config ARM64 
	select HAVE_HW_BREAKPOINT if PERF_EVENTS

	select HAVE_IOREMAP_PROT

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_LIVEPATCH

	select HAVE_MOD_ARCH_SPECIFIC

	select HAVE_NMI

	select HAVE_PERF_EVENTS
@@ -240,6 +241,7 @@ config ARM64 
	select HAVE_PERF_USER_STACK_DUMP

	select HAVE_PREEMPT_DYNAMIC_KEY

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_RELIABLE_STACKTRACE

	select HAVE_POSIX_CPU_TIMERS_TASK_WORK

	select HAVE_FUNCTION_ARG_ACCESS_API

	select MMU_GATHER_RCU_TABLE_FREE
@@ -278,6 +280,7 @@ config ARM64 
	select HAVE_SOFTIRQ_ON_OWN_STACK

	select USER_STACKTRACE_SUPPORT

	select VDSO_GETRANDOM

	select VMAP_STACK

	help

	  ARM 64-bit (AArch64) Linux support.
@@ -2498,3 +2501,4 @@ source "drivers/acpi/Kconfig" 


source "arch/arm64/kvm/Kconfig"



source "kernel/livepatch/Kconfig"

arch/arm64/include/asm/assembler.h

+2 −2
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ 
	.macro	disable_step_tsk, flgs, tmp

	tbz	\flgs, #TIF_SINGLESTEP, 9990f

	mrs	\tmp, mdscr_el1

	bic	\tmp, \tmp, #DBG_MDSCR_SS

	bic	\tmp, \tmp, #MDSCR_EL1_SS

	msr	mdscr_el1, \tmp

	isb	// Take effect before a subsequent clear of DAIF.D

9990:
@@ -68,7 +68,7 @@ 
	.macro	enable_step_tsk, flgs, tmp

	tbz	\flgs, #TIF_SINGLESTEP, 9990f

	mrs	\tmp, mdscr_el1

	orr	\tmp, \tmp, #DBG_MDSCR_SS

	orr	\tmp, \tmp, #MDSCR_EL1_SS

	msr	mdscr_el1, \tmp

9990:

	.endm