Commit 71209c96 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: correct the name of mes_pipe structure 



Correct the structure name admgpu_mes_pipe to amdgpu_mes_pipe.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 81508279

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ enum amdgpu_mes_priority_level { 


struct amdgpu_mes_funcs;



enum admgpu_mes_pipe {

enum amdgpu_mes_pipe {

	AMDGPU_MES_SCHED_PIPE = 0,

	AMDGPU_MES_KIQ_PIPE,

	AMDGPU_MAX_MES_PIPES = 2,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+7 −7
Original line number Diff line number Diff line
@@ -800,7 +800,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 
};



static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,

					   enum admgpu_mes_pipe pipe)

					   enum amdgpu_mes_pipe pipe)

{

	int r;

	const struct mes_firmware_header_v1_0 *mes_hdr;
@@ -835,7 +835,7 @@ static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 
}



static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,

						enum admgpu_mes_pipe pipe)

						enum amdgpu_mes_pipe pipe)

{

	int r;

	const struct mes_firmware_header_v1_0 *mes_hdr;
@@ -876,7 +876,7 @@ static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 
}



static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,

					 enum admgpu_mes_pipe pipe)

					 enum amdgpu_mes_pipe pipe)

{

	amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],

			      &adev->mes.data_fw_gpu_addr[pipe],
@@ -974,7 +974,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 


/* This function is for backdoor MES firmware */

static int mes_v11_0_load_microcode(struct amdgpu_device *adev,

				    enum admgpu_mes_pipe pipe, bool prime_icache)

				    enum amdgpu_mes_pipe pipe, bool prime_icache)

{

	int r;

	uint32_t data;
@@ -1046,7 +1046,7 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 
}



static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,

				      enum admgpu_mes_pipe pipe)

				      enum amdgpu_mes_pipe pipe)

{

	int r;

	u32 *eop;
@@ -1257,7 +1257,7 @@ static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 
}



static int mes_v11_0_queue_init(struct amdgpu_device *adev,

				enum admgpu_mes_pipe pipe)

				enum amdgpu_mes_pipe pipe)

{

	struct amdgpu_ring *ring;

	int r;
@@ -1340,7 +1340,7 @@ static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 
}



static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,

				 enum admgpu_mes_pipe pipe)

				 enum amdgpu_mes_pipe pipe)

{

	int r, mqd_size = sizeof(struct v11_compute_mqd);

	struct amdgpu_ring *ring;

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+7 −7
Original line number Diff line number Diff line
@@ -901,7 +901,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 
};



static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,

					   enum admgpu_mes_pipe pipe)

					   enum amdgpu_mes_pipe pipe)

{

	int r;

	const struct mes_firmware_header_v1_0 *mes_hdr;
@@ -935,7 +935,7 @@ static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, 
}



static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,

						enum admgpu_mes_pipe pipe)

						enum amdgpu_mes_pipe pipe)

{

	int r;

	const struct mes_firmware_header_v1_0 *mes_hdr;
@@ -969,7 +969,7 @@ static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 
}



static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,

					 enum admgpu_mes_pipe pipe)

					 enum amdgpu_mes_pipe pipe)

{

	amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],

			      &adev->mes.data_fw_gpu_addr[pipe],
@@ -1075,7 +1075,7 @@ static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) 


/* This function is for backdoor MES firmware */

static int mes_v12_0_load_microcode(struct amdgpu_device *adev,

				    enum admgpu_mes_pipe pipe, bool prime_icache)

				    enum amdgpu_mes_pipe pipe, bool prime_icache)

{

	int r;

	uint32_t data;
@@ -1139,7 +1139,7 @@ static int mes_v12_0_load_microcode(struct amdgpu_device *adev, 
}



static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,

				      enum admgpu_mes_pipe pipe)

				      enum amdgpu_mes_pipe pipe)

{

	int r;

	u32 *eop;
@@ -1360,7 +1360,7 @@ static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev) 
}



static int mes_v12_0_queue_init(struct amdgpu_device *adev,

				enum admgpu_mes_pipe pipe)

				enum amdgpu_mes_pipe pipe)

{

	struct amdgpu_ring *ring;

	int r;
@@ -1460,7 +1460,7 @@ static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) 
}



static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,

				 enum admgpu_mes_pipe pipe)

				 enum amdgpu_mes_pipe pipe)

{

	int r, mqd_size = sizeof(struct v12_compute_mqd);

	struct amdgpu_ring *ring;