Commit 7416cbbc authored by Andi Shyti's avatar Andi Shyti
Browse files

drm/i915/gt: Rename dev_priv to i915 for private data naming consistency 



It has become common practice to refer to the drm_i915_private
structures as "i915". However, there are still instances where
they are referred to as "dev_priv". This inconsistency can make
grepping for information more difficult and does not maintain a
cohesive style throughout the code.

Rename all the "dev_priv" structures in the gt/* directory to
"i915".

Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Acked-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230210150344.1066991-1-andi.shyti@linux.intel.com
parent 1c388da5

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+9 −9
Original line number Diff line number Diff line
@@ -2058,13 +2058,13 @@ static const char *repr_timer(const struct timer_list *t) 
static void intel_engine_print_registers(struct intel_engine_cs *engine,

					 struct drm_printer *m)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *i915 = engine->i915;

	struct intel_engine_execlists * const execlists = &engine->execlists;

	u64 addr;



	if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))

	if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(i915, 4, 7))

		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));

	if (HAS_EXECLISTS(dev_priv)) {

	if (HAS_EXECLISTS(i915)) {

		drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",

			   ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));

		drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
@@ -2085,7 +2085,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, 
			   ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");

	}



	if (GRAPHICS_VER(dev_priv) >= 6) {

	if (GRAPHICS_VER(i915) >= 6) {

		drm_printf(m, "\tRING_IMR:   0x%08x\n",

			   ENGINE_READ(engine, RING_IMR));

		drm_printf(m, "\tRING_ESR:   0x%08x\n",
@@ -2102,15 +2102,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, 
	addr = intel_engine_get_last_batch_head(engine);

	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",

		   upper_32_bits(addr), lower_32_bits(addr));

	if (GRAPHICS_VER(dev_priv) >= 8)

	if (GRAPHICS_VER(i915) >= 8)

		addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);

	else if (GRAPHICS_VER(dev_priv) >= 4)

	else if (GRAPHICS_VER(i915) >= 4)

		addr = ENGINE_READ(engine, RING_DMA_FADD);

	else

		addr = ENGINE_READ(engine, DMA_FADD_I8XX);

	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",

		   upper_32_bits(addr), lower_32_bits(addr));

	if (GRAPHICS_VER(dev_priv) >= 4) {

	if (GRAPHICS_VER(i915) >= 4) {

		drm_printf(m, "\tIPEIR: 0x%08x\n",

			   ENGINE_READ(engine, RING_IPEIR));

		drm_printf(m, "\tIPEHR: 0x%08x\n",
@@ -2120,7 +2120,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, 
		drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));

	}



	if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {

	if (HAS_EXECLISTS(i915) && !intel_engine_uses_guc(engine)) {

		struct i915_request * const *port, *rq;

		const u32 *hws =

			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
@@ -2186,7 +2186,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, 
		}

		rcu_read_unlock();

		i915_sched_engine_active_unlock_bh(engine->sched_engine);

	} else if (GRAPHICS_VER(dev_priv) > 6) {

	} else if (GRAPHICS_VER(i915) > 6) {

		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",

			   ENGINE_READ(engine, RING_PP_DIR_BASE));

		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",

drivers/gpu/drm/i915/gt/intel_gsc.h

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ struct intel_gsc { 
	} intf[INTEL_GSC_NUM_INTERFACES];

};



void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_priv);

void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915);

void intel_gsc_fini(struct intel_gsc *gsc);

void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
 * ignored.

 */



#define HAS_MSLICE_STEERING(dev_priv)	(INTEL_INFO(dev_priv)->has_mslice_steering)

#define HAS_MSLICE_STEERING(i915)	(INTEL_INFO(i915)->has_mslice_steering)



static const char * const intel_steering_types[] = {

	"L3BANK",

drivers/gpu/drm/i915/gt/intel_reset_types.h

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ struct intel_reset { 


	/**

	 * Waitqueue to signal when the reset has completed. Used by clients

	 * that wait for dev_priv->mm.wedged to settle.

	 * that wait for i915->mm.wedged to settle.

	 */

	wait_queue_head_t queue;

drivers/gpu/drm/i915/gt/intel_ring_submission.c

+2 −2
Original line number Diff line number Diff line
@@ -1052,9 +1052,9 @@ static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) 


static void ring_release(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *i915 = engine->i915;



	drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&

	drm_WARN_ON(&i915->drm, GRAPHICS_VER(i915) > 2 &&

		    (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);



	intel_engine_cleanup_common(engine);