Commit 756e58e8 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: remove minimum Dispclk and apply oem panel timing. 



[why & how]
1. apply oem panel timing (not only on OLED)
2. remove MIN_DPP_DISP_CLK request in driver.

This fix will apply for dcn31x but not
sync with DML's output.

Reviewed-by: default avatarOvidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 27238548

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+0 −2
Original line number Diff line number Diff line
@@ -194,8 +194,6 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, 
	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.

	if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)

		new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;

	if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)

		new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;



	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+0 −2
Original line number Diff line number Diff line
@@ -201,8 +201,6 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 
	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.

	if (new_clocks->dppclk_khz < 100000)

		new_clocks->dppclk_khz = 100000;

	if (new_clocks->dispclk_khz < 100000)

		new_clocks->dispclk_khz = 100000;



	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {

		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+2 −1
Original line number Diff line number Diff line
@@ -1066,7 +1066,8 @@ void dce110_edp_backlight_control( 
			DC_LOG_DC("edp_receiver_ready_T9 skipped\n");

	}



	if (!enable && link->dpcd_sink_ext_caps.bits.oled) {

	if (!enable) {

		/*follow oem panel config's requirement*/

		pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;

		msleep(pre_T11_delay);

	}