Commit 758debf3 authored by Matthew Brost's avatar Matthew Brost
Browse files

drm/xe: Mark ComputeCS read mode as UC on iGPU 



RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
structure. Having this as WB blocks ULLS from being enabled. Change to
UC to unblock ULLS on iGPU.

v2:
 - Drop internal communications commnet, bspec is updated

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Fixes: 328e089b ("drm/xe: Leverage ComputeCS read L3 caching")
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Acked-by: default avatarMichal Mrozek <michal.mrozek@intel.com>
Reviewed-by: default avatarStuart Summers <stuart.summers@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250114002507.114087-1-matthew.brost@intel.com
parent 75d37750

drivers/gpu/drm/xe/xe_hw_engine.c

+1 −1
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe) 
	 * Bspec: 72161

	 */

	const u8 mocs_write_idx = gt->mocs.uc_index;

	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&

	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&

				 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?

				 gt->mocs.wb_index : gt->mocs.uc_index;

	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |