Commit 75faf216 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g056: Add entries for the DMACs 



Add clock and reset entries for the DMAC IPs.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125221420.288809-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e6810000

drivers/clk/renesas/r9a09g056-cpg.c

+19 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ enum clk_ids { 
	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV8,

	CLK_PLLDTY_DIV16,

	CLK_PLLDTY_RCPU,

	CLK_PLLDTY_RCPU_DIV4,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_ISP,
@@ -184,6 +186,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),

	DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
@@ -231,6 +235,16 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
};



static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {

	DEF_MOD("dmac_0_aclk",			CLK_PLLCM33_GEAR, 0, 0, 0, 0,

						BUS_MSTOP(5, BIT(9))),

	DEF_MOD("dmac_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,

						BUS_MSTOP(3, BIT(2))),

	DEF_MOD("dmac_2_aclk",			CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,

						BUS_MSTOP(3, BIT(3))),

	DEF_MOD("dmac_3_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,

						BUS_MSTOP(10, BIT(11))),

	DEF_MOD("dmac_4_aclk",			CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,

						BUS_MSTOP(10, BIT(12))),

	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,

						BUS_MSTOP(3, BIT(5))),

	DEF_MOD("gtm_0_pclk",			CLK_PLLCM33_DIV16, 4, 3, 2, 3,
@@ -401,6 +415,11 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 


static const struct rzv2h_reset r9a09g056_resets[] __initconst = {

	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */

	DEF_RST(3, 1, 1, 2),		/* DMAC_0_ARESETN */

	DEF_RST(3, 2, 1, 3),		/* DMAC_1_ARESETN */

	DEF_RST(3, 3, 1, 4),		/* DMAC_2_ARESETN */

	DEF_RST(3, 4, 1, 5),		/* DMAC_3_ARESETN */

	DEF_RST(3, 5, 1, 6),		/* DMAC_4_ARESETN */

	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */

	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */

	DEF_RST(6, 13, 2, 30),		/* GTM_0_PRESETZ */