Unverified Commit 76ebfa37 authored by Gabor Juhos's avatar Gabor Juhos Committed by Mark Brown
Browse files

spi: spi-qpic-snand: extend FIELD_PREP() macro usage 



Large part of the code uses the FIELD_PREP() macro already to construct
values to be written to hardware registers. Change the code to use also
the macro for more registers of which the corresponding bitmasks are
defined already.

This makes the code more readable. It also syncs the affected
codes with their counterparts in the 'qcom_nandc' driver, so it
makes it easier to spot the differences between the two
implementations.

No functional changes intended.

Signed-off-by: default avatarGabor Juhos <j4g8y7@gmail.com>
Reviewed-by: default avatarMd Sadre Alam <quic_mdalam@quicinc.com>
Link: https://patch.msgid.link/20250515-qpic-snand-use-bitmasks-v1-2-11729aeae73b@gmail.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 2abf107d

drivers/spi/spi-qpic-snand.c

+7 −7
Original line number Diff line number Diff line
@@ -130,9 +130,9 @@ static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc, 
					int is_last_read_loc)

{

	__le32 locreg_val;

	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |

		  ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)

		  << READ_LOCATION_LAST));

	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |

		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |

		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);



	locreg_val = cpu_to_le32(val);
@@ -151,9 +151,9 @@ static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc, 
				       int is_last_read_loc)

{

	__le32 locreg_val;

	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |

		  ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)

		  << READ_LOCATION_LAST));

	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |

		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |

		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);



	locreg_val = cpu_to_le32(val);
@@ -352,7 +352,7 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) 
			       FIELD_PREP(ECC_MODE_MASK, 0) |

			       FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);



	ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;

	ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);

	ecc_cfg->clrflashstatus = FS_READY_BSY_N;

	ecc_cfg->clrreadstatus = 0xc0;