Unverified Commit 794f8770 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v6.9/dt-warnings-signed' of... 

Merge tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/late

Update TI clksel clocks to use reg

Updates for TI clksel clocks to use the standard reg property instead of
the non-standard ti,bit-shift legacy property.

There are still lots of TI composite clock related devicetree warnings for
missing bindings, and overlapping reg properties. We have grouped some of
the TI composite clocks under the clksel clock node, but did not consider
the reg property issue. Let's update the existing users before we continue
grouping more of the composite clocks.

* tag 'omap-for-v6.9/dt-warnings-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
  ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
  clk: ti: Improve clksel clock bit parsing for reg property
  clk: ti: Handle possible address in the node name

Link: https://lore.kernel.org/r/pull-1709102378-94138@atomide.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d206a76d 808e6530

arch/arm/boot/dts/ti/omap/am33xx-clocks.dtsi

+22 −17
Original line number Diff line number Diff line
@@ -108,30 +108,31 @@ clock@664 { 
		compatible = "ti,clksel";

		reg = <0x664>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		ehrpwm0_tbclk: clock-ehrpwm0-tbclk {

		ehrpwm0_tbclk: clock-ehrpwm0-tbclk@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "ehrpwm0_tbclk";

			clocks = <&l4ls_gclk>;

			ti,bit-shift = <0>;

		};



		ehrpwm1_tbclk: clock-ehrpwm1-tbclk {

		ehrpwm1_tbclk: clock-ehrpwm1-tbclk@1 {

			reg = <1>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "ehrpwm1_tbclk";

			clocks = <&l4ls_gclk>;

			ti,bit-shift = <1>;

		};



		ehrpwm2_tbclk: clock-ehrpwm2-tbclk {

		ehrpwm2_tbclk: clock-ehrpwm2-tbclk@2 {

			reg = <2>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "ehrpwm2_tbclk";

			clocks = <&l4ls_gclk>;

			ti,bit-shift = <2>;

		};

	};

};
@@ -566,17 +567,19 @@ clock@52c { 
		compatible = "ti,clksel";

		reg = <0x52c>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {

		gfx_fclk_clksel_ck: clock-gfx-fclk-clksel@1 {

			reg = <1>;

			#clock-cells = <0>;

			compatible = "ti,mux-clock";

			clock-output-names = "gfx_fclk_clksel_ck";

			clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;

			ti,bit-shift = <1>;

		};



		gfx_fck_div_ck: clock-gfx-fck-div {

		gfx_fck_div_ck: clock-gfx-fck-div@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,divider-clock";

			clock-output-names = "gfx_fck_div_ck";
@@ -589,30 +592,32 @@ clock@700 { 
		compatible = "ti,clksel";

		reg = <0x700>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		sysclkout_pre_ck: clock-sysclkout-pre {

		sysclkout_pre_ck: clock-sysclkout-pre@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,mux-clock";

			clock-output-names = "sysclkout_pre_ck";

			clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;

		};



		clkout2_div_ck: clock-clkout2-div {

		clkout2_div_ck: clock-clkout2-div@3 {

			reg = <3>;

			#clock-cells = <0>;

			compatible = "ti,divider-clock";

			clock-output-names = "clkout2_div_ck";

			clocks = <&sysclkout_pre_ck>;

			ti,bit-shift = <3>;

			ti,max-div = <8>;

		};



		clkout2_ck: clock-clkout2 {

		clkout2_ck: clock-clkout2@7 {

			reg = <7>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "clkout2_ck";

			clocks = <&clkout2_div_ck>;

			ti,bit-shift = <7>;

		};

	};

};

arch/arm/boot/dts/ti/omap/am35xx-clocks.dtsi

+10 −8
Original line number Diff line number Diff line
@@ -66,22 +66,23 @@ clock@a10 { 
		compatible = "ti,clksel";

		reg = <0xa10>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		ipss_ick: clock-ipss-ick {

		ipss_ick: clock-ipss-ick@4 {

			reg = <4>;

			#clock-cells = <0>;

			compatible = "ti,am35xx-interface-clock";

			clock-output-names = "ipss_ick";

			clocks = <&core_l3_ick>;

			ti,bit-shift = <4>;

		};



		uart4_ick_am35xx: clock-uart4-ick-am35xx {

		uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {

			reg = <23>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "uart4_ick_am35xx";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <23>;

		};

	};
@@ -101,14 +102,15 @@ clock@a00 { 
		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		uart4_fck_am35xx: clock-uart4-fck-am35xx {

		uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {

			reg = <23>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "uart4_fck_am35xx";

			clocks = <&core_48m_fck>;

			ti,bit-shift = <23>;

		};

	};

};

arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi

+28 −24
Original line number Diff line number Diff line
@@ -50,30 +50,31 @@ clock@a00 { 
		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		d2d_26m_fck: clock-d2d-26m-fck {

		d2d_26m_fck: clock-d2d-26m-fck@3 {

			reg = <3>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "d2d_26m_fck";

			clocks = <&sys_ck>;

			ti,bit-shift = <3>;

		};



		fshostusb_fck: clock-fshostusb-fck {

		fshostusb_fck: clock-fshostusb-fck@5 {

			reg = <5>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "fshostusb_fck";

			clocks = <&core_48m_fck>;

			ti,bit-shift = <5>;

		};



		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {

		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,composite-no-wait-gate-clock";

			clock-output-names = "ssi_ssr_gate_fck_3430es1";

			clocks = <&corex2_fck>;

			ti,bit-shift = <0>;

		};

	};
@@ -81,23 +82,24 @@ clock@a40 { 
		compatible = "ti,clksel";

		reg = <0xa40>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {

		ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {

			reg = <8>;

			#clock-cells = <0>;

			compatible = "ti,composite-divider-clock";

			clock-output-names = "ssi_ssr_div_fck_3430es1";

			clocks = <&corex2_fck>;

			ti,bit-shift = <8>;

			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;

		};



		usb_l4_div_ick: clock-usb-l4-div-ick {

		usb_l4_div_ick: clock-usb-l4-div-ick@4 {

			reg = <4>;

			#clock-cells = <0>;

			compatible = "ti,composite-divider-clock";

			clock-output-names = "usb_l4_div_ick";

			clocks = <&l4_ick>;

			ti,bit-shift = <4>;

			ti,max-div = <1>;

			ti,index-starts-at-one;

		};
@@ -121,38 +123,39 @@ clock@a10 { 
		compatible = "ti,clksel";

		reg = <0xa10>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {

		hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {

			reg = <4>;

			#clock-cells = <0>;

			compatible = "ti,omap3-no-wait-interface-clock";

			clock-output-names = "hsotgusb_ick_3430es1";

			clocks = <&core_l3_ick>;

			ti,bit-shift = <4>;

		};



		fac_ick: clock-fac-ick {

		fac_ick: clock-fac-ick@8 {

			reg = <8>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "fac_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <8>;

		};



		ssi_ick: clock-ssi-ick-3430es1 {

		ssi_ick: clock-ssi-ick-3430es1@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,omap3-no-wait-interface-clock";

			clock-output-names = "ssi_ick_3430es1";

			clocks = <&ssi_l4_ick>;

			ti,bit-shift = <0>;

		};



		usb_l4_gate_ick: clock-usb-l4-gate-ick {

		usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {

			reg = <5>;

			#clock-cells = <0>;

			compatible = "ti,composite-interface-clock";

			clock-output-names = "usb_l4_gate_ick";

			clocks = <&l4_ick>;

			ti,bit-shift = <5>;

		};

	};
@@ -174,14 +177,15 @@ clock@e00 { 
		compatible = "ti,clksel";

		reg = <0xe00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {

		dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "dss1_alwon_fck_3430es1";

			clocks = <&dpll4_m4x2_ck>;

			ti,bit-shift = <0>;

			ti,set-rate-parent;

		};

	};

arch/arm/boot/dts/ti/omap/omap34xx-omap36xx-clocks.dtsi

+46 −40
Original line number Diff line number Diff line
@@ -17,46 +17,47 @@ clock@a14 { 
		compatible = "ti,clksel";

		reg = <0xa14>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		aes1_ick: clock-aes1-ick {

		aes1_ick: clock-aes1-ick@3 {

			reg = <3>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "aes1_ick";

			clocks = <&security_l4_ick2>;

			ti,bit-shift = <3>;

		};



		rng_ick: clock-rng-ick {

		rng_ick: clock-rng-ick@2 {

			reg = <2>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "rng_ick";

			clocks = <&security_l4_ick2>;

			ti,bit-shift = <2>;

		};



		sha11_ick: clock-sha11-ick {

		sha11_ick: clock-sha11-ick@1 {

			reg = <1>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "sha11_ick";

			clocks = <&security_l4_ick2>;

			ti,bit-shift = <1>;

		};



		des1_ick: clock-des1-ick {

		des1_ick: clock-des1-ick@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "des1_ick";

			clocks = <&security_l4_ick2>;

			ti,bit-shift = <0>;

		};



		pka_ick: clock-pka-ick {

		pka_ick: clock-pka-ick@4 {

			reg = <4>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "pka_ick";

			clocks = <&security_l3_ick>;

			ti,bit-shift = <4>;

		};

	};
@@ -65,23 +66,24 @@ clock@f00 { 
		compatible = "ti,clksel";

		reg = <0xf00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		cam_mclk: clock-cam-mclk {

		cam_mclk: clock-cam-mclk@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "cam_mclk";

			clocks = <&dpll4_m5x2_ck>;

			ti,bit-shift = <0>;

			ti,set-rate-parent;

		};



		csi2_96m_fck: clock-csi2-96m-fck {

		csi2_96m_fck: clock-csi2-96m-fck@1 {

			reg = <1>;

			#clock-cells = <0>;

			compatible = "ti,gate-clock";

			clock-output-names = "csi2_96m_fck";

			clocks = <&core_96m_fck>;

			ti,bit-shift = <1>;

		};

	};
@@ -105,46 +107,47 @@ clock@a10 { 
		compatible = "ti,clksel";

		reg = <0xa10>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		icr_ick: clock-icr-ick {

		icr_ick: clock-icr-ick@29 {

			reg = <29>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "icr_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <29>;

		};



		des2_ick: clock-des2-ick {

		des2_ick: clock-des2-ick@26 {

			reg = <26>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "des2_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <26>;

		};



		mspro_ick: clock-mspro-ick {

		mspro_ick: clock-mspro-ick@23 {

			reg = <23>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "mspro_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <23>;

		};



		mailboxes_ick: clock-mailboxes-ick {

		mailboxes_ick: clock-mailboxes-ick@7 {

			reg = <7>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "mailboxes_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <7>;

		};



		sad2d_ick: clock-sad2d-ick {

		sad2d_ick: clock-sad2d-ick@3 {

			reg = <3>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "sad2d_ick";

			clocks = <&l3_ick>;

			ti,bit-shift = <3>;

		};

	};
@@ -160,22 +163,23 @@ clock@c00 { 
		compatible = "ti,clksel";

		reg = <0xc00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		sr1_fck: clock-sr1-fck {

		sr1_fck: clock-sr1-fck@6 {

			reg = <6>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "sr1_fck";

			clocks = <&sys_ck>;

			ti,bit-shift = <6>;

		};



		sr2_fck: clock-sr2-fck {

		sr2_fck: clock-sr2-fck@7 {

			reg = <7>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "sr2_fck";

			clocks = <&sys_ck>;

			ti,bit-shift = <7>;

		};

	};
@@ -228,22 +232,23 @@ clock@a00 { 
		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		modem_fck: clock-modem-fck {

		modem_fck: clock-modem-fck@31 {

			reg = <31>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "modem_fck";

			clocks = <&sys_ck>;

			ti,bit-shift = <31>;

		};



		mspro_fck: clock-mspro-fck {

		mspro_fck: clock-mspro-fck@23 {

			reg = <23>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "mspro_fck";

			clocks = <&core_96m_fck>;

			ti,bit-shift = <23>;

		};

	};
@@ -252,14 +257,15 @@ clock@a18 { 
		compatible = "ti,clksel";

		reg = <0xa18>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#ssize-cells = <0>;



		mad2d_ick: clock-mad2d-ick {

		mad2d_ick: clock-mad2d-ick@3 {

			reg = <3>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "mad2d_ick";

			clocks = <&l3_ick>;

			ti,bit-shift = <3>;

		};

	};

arch/arm/boot/dts/ti/omap/omap36xx-am35xx-omap3430es2plus-clocks.dtsi

+16 −12
Original line number Diff line number Diff line
@@ -138,14 +138,15 @@ clock@a18 { 
		compatible = "ti,clksel";

		reg = <0xa18>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		usbtll_ick: clock-usbtll-ick {

		usbtll_ick: clock-usbtll-ick@2 {

			reg = <2>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "usbtll_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <2>;

		};

	};
@@ -153,14 +154,15 @@ clock@a10 { 
		compatible = "ti,clksel";

		reg = <0xa10>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		mmchs3_ick: clock-mmchs3-ick {

		mmchs3_ick: clock-mmchs3-ick@30 {

			reg = <30>;

			#clock-cells = <0>;

			compatible = "ti,omap3-interface-clock";

			clock-output-names = "mmchs3_ick";

			clocks = <&core_l4_ick>;

			ti,bit-shift = <30>;

		};

	};
@@ -168,14 +170,15 @@ clock@a00 { 
		compatible = "ti,clksel";

		reg = <0xa00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		mmchs3_fck: clock-mmchs3-fck {

		mmchs3_fck: clock-mmchs3-fck@30 {

			reg = <30>;

			#clock-cells = <0>;

			compatible = "ti,wait-gate-clock";

			clock-output-names = "mmchs3_fck";

			clocks = <&core_96m_fck>;

			ti,bit-shift = <30>;

		};

	};
@@ -183,14 +186,15 @@ clock@e00 { 
		compatible = "ti,clksel";

		reg = <0xe00>;

		#clock-cells = <2>;

		#address-cells = <0>;

		#address-cells = <1>;

		#size-cells = <0>;



		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {

		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {

			reg = <0>;

			#clock-cells = <0>;

			compatible = "ti,dss-gate-clock";

			clock-output-names = "dss1_alwon_fck_3430es2";

			clocks = <&dpll4_m4x2_ck>;

			ti,bit-shift = <0>;

			ti,set-rate-parent;

		};

	};