Commit 7a637e5e authored by Danylo Piliaiev's avatar Danylo Piliaiev Committed by Rob Clark
Browse files

drm/msm: Expose uche trap base via uapi 



This adds MSM_PARAM_UCHE_TRAP_BASE that will be used by Mesa
implementation for VK_KHR_shader_clock and GL_ARB_shader_clock.

Signed-off-by: default avatarDanylo Piliaiev <dpiliaiev@igalia.com>
Patchwork: https://patchwork.freedesktop.org/patch/627036/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 855e9d0f

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+4 −2
Original line number Diff line number Diff line
@@ -251,8 +251,8 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
		gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07);



	/* Disable L2 bypass to avoid UCHE out of bounds errors */

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000);

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000);

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));

	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));



	gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |

			(adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));
@@ -693,6 +693,8 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
	if (ret)

		goto fail;



	adreno_gpu->uche_trap_base = 0xffff0000ffff0000ull;



	if (!gpu->aspace) {

		/* TODO we think it is possible to configure the GPU to

		 * restrict access to VRAM carveout.  But the required

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+6 −4
Original line number Diff line number Diff line
@@ -750,10 +750,10 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);



	/* Disable L2 bypass in the UCHE */

	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000);

	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF);

	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000);

	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF);

	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));

	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));

	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));

	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));



	/* Set the GMEM VA range (0 to gpu->gmem) */

	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
@@ -1805,5 +1805,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 
	adreno_gpu->ubwc_config.macrotile_mode = 0;

	adreno_gpu->ubwc_config.ubwc_swizzle = 0x7;



	adreno_gpu->uche_trap_base = 0x0001ffffffff0000ull;



	return gpu;

}

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+7 −5
Original line number Diff line number Diff line
@@ -1123,12 +1123,12 @@ static int hw_init(struct msm_gpu *gpu) 


	/* Disable L2 bypass in the UCHE */

	if (adreno_is_a7xx(adreno_gpu)) {

		gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu);

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu);

		gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);

	} else {

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu);

		gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu);

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu);

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0);

		gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);

		gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);

	}



	if (!(adreno_is_a650_family(adreno_gpu) ||
@@ -2533,6 +2533,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 
		}

	}



	adreno_gpu->uche_trap_base = 0x1fffffffff000ull;



	if (gpu->aspace)

		msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,

				a6xx_fault_handler);

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+3 −0
Original line number Diff line number Diff line
@@ -385,6 +385,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, 
	case MSM_PARAM_MACROTILE_MODE:

		*value = adreno_gpu->ubwc_config.macrotile_mode;

		return 0;

	case MSM_PARAM_UCHE_TRAP_BASE:

		*value = adreno_gpu->uche_trap_base;

		return 0;

	default:

		DBG("%s: invalid param: %u", gpu->name, param);

		return -EINVAL;

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+2 −0
Original line number Diff line number Diff line
@@ -253,6 +253,8 @@ struct adreno_gpu { 
	bool gmu_is_wrapper;



	bool has_ray_tracing;



	u64 uche_trap_base;

};

#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)