Commit 7b88453a authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Change get_enabled_mask signature 



Use smu_feature_bits instead of uint64_t pointer and operate on
feature bits.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e37fb0f8

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+13 −4
Original line number Diff line number Diff line
@@ -1646,7 +1646,7 @@ static int smu_smc_hw_setup(struct smu_context *smu) 
{

	struct amdgpu_device *adev = smu->adev;

	uint8_t pcie_gen = 0, pcie_width = 0;

	uint64_t features_supported;

	struct smu_feature_bits features_supported;

	int ret = 0;



	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
@@ -1807,7 +1807,7 @@ static int smu_smc_hw_setup(struct smu_context *smu) 
		return ret;

	}

	smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED,

				  (unsigned long *)&features_supported);

			     features_supported.bits);



	if (!smu_is_dpm_running(smu))

		dev_info(adev->dev, "dpm has been disabled\n");
@@ -3152,10 +3152,19 @@ static int smu_read_sensor(void *handle, 
		*((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;

		*size = 4;

		break;

	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:

		ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);

	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: {

		struct smu_feature_bits feature_mask;

		uint32_t features[2];



		/* TBD: need to handle for > 64 bits */

		ret = smu_feature_get_enabled_mask(smu, &feature_mask);

		if (!ret) {

			smu_feature_bits_to_arr32(&feature_mask, features, 64);

			*(uint64_t *)data = *(uint64_t *)features;

		}

		*size = 8;

		break;

	}

	case AMDGPU_PP_SENSOR_UVD_POWER:

		*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;

		*size = 4;

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+8 −1
Original line number Diff line number Diff line
@@ -1229,7 +1229,8 @@ struct pptable_funcs { 
	 *                    on the SMU.

	 * &feature_mask: Enabled feature mask.

	 */

	int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);

	int (*get_enabled_mask)(struct smu_context *smu,

				struct smu_feature_bits *feature_mask);



	/**

	 * @feature_is_enabled: Test if a feature is enabled.
@@ -2061,6 +2062,12 @@ static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, 
	return bitmap_empty(bits->bits, nbits);

}



static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits,

					 unsigned int nbits)

{

	return bitmap_full(bits->bits, nbits);

}



static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,

					 const unsigned long *src,

					 unsigned int nbits)

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+3 −4
Original line number Diff line number Diff line
@@ -1527,15 +1527,14 @@ static int arcturus_set_performance_level(struct smu_context *smu, 
static bool arcturus_is_dpm_running(struct smu_context *smu)

{

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];

	struct smu_feature_bits feature_enabled;



	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);

	if (ret)

		return false;



	smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

	return smu_feature_bits_test_mask(&feature_enabled,

					  arcturus_dpm_features.bits);

}



static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

+7 −7
Original line number Diff line number Diff line
@@ -363,8 +363,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) 
{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];

	struct smu_feature_bits feature_enabled;



	/* we need to re-init after suspend so return false */

	if (adev->in_suspend)
@@ -381,8 +380,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) 
		cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,

			&cyan_skillfish_sclk_default);



	smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

	return smu_feature_bits_test_mask(&feature_enabled,

					  cyan_skillfish_dpm_features.bits);

}



static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,
@@ -569,12 +568,13 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu, 
	return 0;

}



static int cyan_skillfish_get_enabled_mask(struct smu_context *smu,

					   uint64_t *feature_mask)

static int

cyan_skillfish_get_enabled_mask(struct smu_context *smu,

				struct smu_feature_bits *feature_mask)

{

	if (!feature_mask)

		return -EINVAL;

	memset(feature_mask, 0xff, sizeof(*feature_mask));

	smu_feature_bits_fill(feature_mask);



	return 0;

}

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+3 −4
Original line number Diff line number Diff line
@@ -1621,15 +1621,14 @@ static int navi10_display_config_changed(struct smu_context *smu) 
static bool navi10_is_dpm_running(struct smu_context *smu)

{

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];

	struct smu_feature_bits feature_enabled;



	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);

	if (ret)

		return false;



	smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

	return smu_feature_bits_test_mask(&feature_enabled,

					  navi10_dpm_features.bits);

}



static int navi10_get_fan_speed_rpm(struct smu_context *smu,