Commit 7bb46e03 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/reg: fix pipe data/link m/n register style 



Adhere to the style described at the top of i915_reg.h.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/99fb1c8aabb7646ca2565db0b969cf15d9103318.1725974820.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 2ac6a84b

drivers/gpu/drm/i915/i915_reg.h

+21 −18
Original line number Diff line number Diff line
@@ -2160,32 +2160,35 @@ 
# define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)



#define _PIPEA_DATA_M1		0x60030

#define _PIPEA_DATA_N1		0x60034

#define _PIPEA_DATA_M2		0x60038

#define _PIPEA_DATA_N2		0x6003c

#define _PIPEA_LINK_M1		0x60040

#define _PIPEA_LINK_N1		0x60044

#define _PIPEA_LINK_M2		0x60048

#define _PIPEA_LINK_N2		0x6004c



/* PIPEB timing regs are same start from 0x61000 */



#define _PIPEB_DATA_M1		0x61030

#define _PIPEB_DATA_N1		0x61034

#define _PIPEB_DATA_M2		0x61038

#define _PIPEB_DATA_N2		0x6103c

#define _PIPEB_LINK_M1		0x61040

#define _PIPEB_LINK_N1		0x61044

#define _PIPEB_LINK_M2		0x61048

#define _PIPEB_LINK_N2		0x6104c



#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)



#define _PIPEA_DATA_N1		0x60034

#define _PIPEB_DATA_N1		0x61034

#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)



#define _PIPEA_DATA_M2		0x60038

#define _PIPEB_DATA_M2		0x61038

#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)



#define _PIPEA_DATA_N2		0x6003c

#define _PIPEB_DATA_N2		0x6103c

#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)



#define _PIPEA_LINK_M1		0x60040

#define _PIPEB_LINK_M1		0x61040

#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)



#define _PIPEA_LINK_N1		0x60044

#define _PIPEB_LINK_N1		0x61044

#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)



#define _PIPEA_LINK_M2		0x60048

#define _PIPEB_LINK_M2		0x61048

#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)



#define _PIPEA_LINK_N2		0x6004c

#define _PIPEB_LINK_N2		0x6104c

#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)



/* CPU panel fitter */