Commit 7bc22763 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-airoha-fix-pse-memory-configuration' 

Lorenzo Bianconi says:

====================
net: airoha: Fix PSE memory configuration

Align PSE memory configuration to vendor SDK.
Increase initial value of PSE reserved memory in
airoha_fe_pse_ports_init() by the value used for the second Packet
Processor Engine (PPE2).
Do not overwrite the default value for the number of PSE reserved pages
in airoha_fe_set_pse_oq_rsv().
These changes fix issues which are not visible to the user.

v1: https://lore.kernel.org/20240930-airoha-eth-pse-fix-v1-0-f41f2f35abb9@kernel.org
====================

Link: https://patch.msgid.link/20241001-airoha-eth-pse-fix-v2-0-9a56cdffd074@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 7d68b6f6 8e38e08f

drivers/net/ethernet/mediatek/airoha_eth.c

+14 −6
Original line number Diff line number Diff line
@@ -1116,17 +1116,23 @@ static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 
		      PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK);

}



static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)

{

	u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);



	return FIELD_GET(PSE_ALLRSV_MASK, val);

}



static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,

				    u32 port, u32 queue, u32 val)

{

	u32 orig_val, tmp, all_rsv, fq_limit;

	u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);

	u32 tmp, all_rsv, fq_limit;



	airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);



	/* modify all rsv */

	orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);

	tmp = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);

	all_rsv = FIELD_GET(PSE_ALLRSV_MASK, tmp);

	all_rsv = airoha_fe_get_pse_all_rsv(eth);

	all_rsv += (val - orig_val);

	airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,

		      FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));
@@ -1166,11 +1172,13 @@ static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 
		[FE_PSE_PORT_GDM4] = 2,

		[FE_PSE_PORT_CDM5] = 2,

	};

	u32 all_rsv;

	int q;



	all_rsv = airoha_fe_get_pse_all_rsv(eth);

	/* hw misses PPE2 oq rsv */

	airoha_fe_set(eth, REG_FE_PSE_BUF_SET,

		      PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2]);

	all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2];

	airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv);



	/* CMD1 */

	for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)