Commit 7d59465d authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Add 3DLUT DMA broadcast support 



[WHY&HOW]
A single HUBP can be used to fetch 3DLUT and broadcast to a
single HUBP.  Add logic to select the top pipe for a given
plane and use it's HUBP as the broadcast source for multiple
MPC's.

Reviewed-by: default avatarIlya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: default avatarDillon Varone <Dillon.Varone@amd.com>
Signed-off-by: default avatarChuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 60e8ffaf

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −1
Original line number Diff line number Diff line
@@ -4617,7 +4617,7 @@ static void commit_planes_for_stream(struct dc *dc, 
						srf_updates[i].cm->flags.bits.lut3d_enable &&

						srf_updates[i].cm->flags.bits.lut3d_dma_enable &&

						dc->hwss.trigger_3dlut_dma_load)

					dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);

					dc->hwss.trigger_3dlut_dma_load(pipe_ctx);



				/*program triple buffer after lock based on flip type*/

				if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

+64 −44
Original line number Diff line number Diff line
@@ -369,12 +369,14 @@ void dcn401_init_hw(struct dc *dc) 
	}

}



void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx)

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx);

	struct hubp *primary_hubp = primary_dpp_pipe_ctx ?

			primary_dpp_pipe_ctx->plane_res.hubp : NULL;



	if (hubp->funcs->hubp_enable_3dlut_fl) {

		hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

	if (primary_hubp && primary_hubp->funcs->hubp_enable_3dlut_fl) {

		primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);

	}

}
@@ -382,8 +384,11 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 
				const struct dc_plane_state *plane_state)

{

	struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc;

	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx);

	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct hubp *primary_hubp =	primary_dpp_pipe_ctx ?

			primary_dpp_pipe_ctx->plane_res.hubp : NULL;

	const struct dc_plane_cm *cm = &plane_state->cm;

	int mpcc_id = hubp->inst;

	struct mpc *mpc = dc->res_pool->mpc;
@@ -481,9 +486,11 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 
			mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id);



		if (mpc->funcs->update_3dlut_fast_load_select)

			mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst);

			mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, primary_hubp->inst);



		/* HUBP */

		if (primary_hubp->inst == hubp->inst) {

			/* only program if this is the primary dpp pipe for the given plane */

			if (hubp->funcs->hubp_program_3dlut_fl_config)

				hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma);
@@ -501,6 +508,20 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 
				lut_enable = false;

				result = false;

			}

		} else {

			/* re-trigger priamry HUBP to load 3DLUT */

			if (primary_hubp->funcs->hubp_enable_3dlut_fl) {

				primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);

			}



			/* clear FL setup on this pipe's HUBP */

			memset(&lut3d_dma, 0, sizeof(lut3d_dma));

			if (hubp->funcs->hubp_program_3dlut_fl_config)

				hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma);



			if (hubp->funcs->hubp_enable_3dlut_fl)

				hubp->funcs->hubp_enable_3dlut_fl(hubp, false);

		}

	} else {

		/* Legacy (Host) Load Mode */

		memset(&m_lut_params, 0, sizeof(m_lut_params));
@@ -1809,42 +1830,41 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) 
	 * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless

	 * of whether OTG lock is currently being held or not.

	 */

	struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };

	struct pipe_ctx *odm_pipe, *mpc_pipe;

	int i, wa_pipe_ct = 0;



	for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) {

		for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) {

			if (mpc_pipe->plane_state &&

					mpc_pipe->plane_state->cm.flags.bits.lut3d_enable &&

					mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) {

				wa_pipes[wa_pipe_ct++] = mpc_pipe;

			}

		}

	const struct pipe_ctx *otg_master_pipe_ctx = resource_get_otg_master(pipe_ctx);

	struct timing_generator *tg = otg_master_pipe_ctx ?

			otg_master_pipe_ctx->stream_res.tg : NULL;

	const struct pipe_ctx *primary_dpp_pipe_ctx = resource_is_pipe_type(pipe_ctx, DPP_PIPE) ?

			resource_get_primary_dpp_pipe(pipe_ctx) : pipe_ctx;

	struct hubp *primary_hubp = primary_dpp_pipe_ctx ?

			primary_dpp_pipe_ctx->plane_res.hubp : NULL;



	if (!otg_master_pipe_ctx && !tg) {

		return;

	}



	if (wa_pipe_ct > 0) {

		if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

			pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true);

	if (primary_dpp_pipe_ctx &&

			primary_dpp_pipe_ctx->plane_state &&

			primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_enable &&

			primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_dma_enable) {

		if (tg->funcs->set_vupdate_keepout)

			tg->funcs->set_vupdate_keepout(tg, true);



		for (i = 0; i < wa_pipe_ct; ++i) {

			if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

				wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

		if (primary_hubp->funcs->hubp_enable_3dlut_fl) {

			primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);

		}



		pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

		if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status)

			pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false);

		tg->funcs->unlock(tg);

		if (tg->funcs->wait_update_lock_status)

			tg->funcs->wait_update_lock_status(tg, false);



		for (i = 0; i < wa_pipe_ct; ++i) {

			if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl)

				wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true);

		if (primary_hubp->funcs->hubp_enable_3dlut_fl) {

			primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true);

		}



		if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout)

			pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false);

		if (tg->funcs->set_vupdate_keepout)

			tg->funcs->set_vupdate_keepout(tg, false);

	} else {

		pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);

		tg->funcs->unlock(tg);

	}

}

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

+1 −2
Original line number Diff line number Diff line
@@ -41,8 +41,7 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 
bool dcn401_set_output_transfer_func(struct dc *dc,

				struct pipe_ctx *pipe_ctx,

				const struct dc_stream_state *stream);

void dcn401_trigger_3dlut_dma_load(struct dc *dc,

				struct pipe_ctx *pipe_ctx);

void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx);

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

				unsigned int *tmds_div);

enum dc_status dcn401_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

+1 −1
Original line number Diff line number Diff line
@@ -1120,7 +1120,7 @@ struct hw_sequencer_funcs { 
	void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

			enum dc_color_space colorspace,

			uint16_t *matrix, int opp_id);

	void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);

	void (*trigger_3dlut_dma_load)(struct pipe_ctx *pipe_ctx);



	/* VM Related */

	int (*init_sys_ctx)(struct dce_hwseq *hws,