Commit 7f15ee35 authored by Arkadiusz Kubalewski's avatar Arkadiusz Kubalewski Committed by Jakub Kicinski
Browse files

dpll: add reference-sync netlink attribute 



Add new netlink attribute to allow user space configuration of reference
sync pin pairs, where both pins are used to provide one clock signal
consisting of both: base frequency and sync signal.

Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Link: https://patch.msgid.link/20250626135219.1769350-2-arkadiusz.kubalewski@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8c72b2a2

Documentation/driver-api/dpll.rst

+25 −0
Original line number Diff line number Diff line
@@ -253,6 +253,31 @@ the pin. 
  ``DPLL_A_PIN_ESYNC_PULSE``                pulse type of Embedded SYNC

  ========================================= =================================



Reference SYNC

==============



The device may support the Reference SYNC feature, which allows the combination

of two inputs into a input pair. In this configuration, clock signals

from both inputs are used to synchronize the DPLL device. The higher frequency

signal is utilized for the loop bandwidth of the DPLL, while the lower frequency

signal is used to syntonize the output signal of the DPLL device. This feature

enables the provision of a high-quality loop bandwidth signal from an external

source.



A capable input provides a list of inputs that can be bound with to create

Reference SYNC. To control this feature, the user must request a desired

state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or

``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be

bound to only one other pin at any given time.



  ============================== ==========================================

  ``DPLL_A_PIN_REFERENCE_SYNC``  nested attribute for providing info or

                                 requesting configuration of the Reference

                                 SYNC feature

    ``DPLL_A_PIN_ID``            target pin id for Reference SYNC feature

    ``DPLL_A_PIN_STATE``         state of Reference SYNC connection

  ============================== ==========================================



Configuration commands group

============================

Documentation/netlink/specs/dpll.yaml

+19 −0
Original line number Diff line number Diff line
@@ -428,6 +428,15 @@ attribute-sets: 
        doc: |

          A ratio of high to low state of a SYNC signal pulse embedded

          into base clock frequency. Value is in percents.

      -

        name: reference-sync

        type: nest

        multi-attr: true

        nested-attributes: reference-sync

        doc: |

          Capable pin provides list of pins that can be bound to create a

          reference-sync pin pair.



  -

    name: pin-parent-device

    subset-of: pin
@@ -458,6 +467,14 @@ attribute-sets: 
        name: frequency-min

      -

        name: frequency-max

  -

    name: reference-sync

    subset-of: pin

    attributes:

      -

        name: id

      -

        name: state



operations:

  enum-name: dpll_cmd
@@ -598,6 +615,7 @@ operations: 
            - esync-frequency

            - esync-frequency-supported

            - esync-pulse

            - reference-sync



      dump:

        request:
@@ -625,6 +643,7 @@ operations: 
            - parent-pin

            - phase-adjust

            - esync-frequency

            - reference-sync

    -

      name: pin-create-ntf

      doc: Notification about pin appearing

drivers/dpll/dpll_nl.c

+8 −2
Original line number Diff line number Diff line
@@ -24,6 +24,11 @@ const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = { 
	[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),

};



const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {

	[DPLL_A_PIN_ID] = { .type = NLA_U32, },

	[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),

};



/* DPLL_CMD_DEVICE_ID_GET - do */

static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {

	[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
@@ -63,7 +68,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] = 
};



/* DPLL_CMD_PIN_SET - do */

static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY + 1] = {

static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_REFERENCE_SYNC + 1] = {

	[DPLL_A_PIN_ID] = { .type = NLA_U32, },

	[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },

	[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -73,6 +78,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY 
	[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),

	[DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },

	[DPLL_A_PIN_ESYNC_FREQUENCY] = { .type = NLA_U64, },

	[DPLL_A_PIN_REFERENCE_SYNC] = NLA_POLICY_NESTED(dpll_reference_sync_nl_policy),

};



/* Ops table for dpll */
@@ -140,7 +146,7 @@ static const struct genl_split_ops dpll_nl_ops[] = { 
		.doit		= dpll_nl_pin_set_doit,

		.post_doit	= dpll_pin_post_doit,

		.policy		= dpll_pin_set_nl_policy,

		.maxattr	= DPLL_A_PIN_ESYNC_FREQUENCY,

		.maxattr	= DPLL_A_PIN_REFERENCE_SYNC,

		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,

	},

};

drivers/dpll/dpll_nl.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
/* Common nested types */

extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];

extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];

extern const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1];



int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,

		   struct genl_info *info);

include/uapi/linux/dpll.h

+1 −0
Original line number Diff line number Diff line
@@ -249,6 +249,7 @@ enum dpll_a_pin { 
	DPLL_A_PIN_ESYNC_FREQUENCY,

	DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,

	DPLL_A_PIN_ESYNC_PULSE,

	DPLL_A_PIN_REFERENCE_SYNC,



	__DPLL_A_PIN_MAX,

	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)