Unverified Commit 7f5e9ca0 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd
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clk: clocking-wizard: Fix the round rate handling for versal 



Fix the `clk_round_rate` implementation for Versal platforms by calling
the Versal-specific divider calculation helper. The existing code used
the generic divider routine, which results in incorrect round rate.

Fixes: 7681f64e ("clk: clocking-wizard: calculate dividers fractional parts")
Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20250625054114.28273-1-shubhrajyoti.datta@amd.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 264200cc

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

+1 −1
Original line number Diff line number Diff line
@@ -669,7 +669,7 @@ static long clk_wzrd_ver_round_rate_all(struct clk_hw *hw, unsigned long rate, 
	u32 m, d, o, div, f;

	int err;



	err = clk_wzrd_get_divisors(hw, rate, *prate);

	err = clk_wzrd_get_divisors_ver(hw, rate, *prate);

	if (err)

		return err;