Commit 7f751be5 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'amd-drm-next-6.14-2025-01-24' of... 

Merge tag 'amd-drm-next-6.14-2025-01-24' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-6.14-2025-01-24:

amdgpu:
- Documentation fixes
- SMU 13.x fixes
- SR-IOV fix
- Display fix
- PCIe calculation fix
- MES 12 fix
- HUBP fix
- Cursor fix
- Enforce isolation fixes
- GFX 12 fix
- Use drm scheduler API helper rather than open coding it
- Mark some debugging parameters as unsafe
- PSP 14.x fix
- Add cleaner shader support for gfx12
- Add subvp debugging flag
- SDMA 4.4.x fix
- Clarify some kernel log messages
- clang fix
- PCIe lane reporting fix
- Documentation fix

amdkfd:
- Mark some debugging parameters as unsafe
- Fix partial migration handling
- Trap handler updates

Signed-off-by: default avatarSimona Vetter <simona.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250124152153.3861868-1-alexander.deucher@amd.com
parents 37f332ea 024771f3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+122 −34
Original line number Diff line number Diff line
@@ -2365,8 +2365,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 
		break;

	}



	DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,

		  ip_block_version->funcs->name);

	dev_info(adev->dev, "detected ip block number %d <%s>\n",

		 adev->num_ip_blocks, ip_block_version->funcs->name);



	adev->ip_blocks[adev->num_ip_blocks].adev = adev;
@@ -6157,6 +6157,44 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev, 
	}

}



/**

 * amdgpu_device_gpu_bandwidth - find the bandwidth of the GPU

 *

 * @adev: amdgpu_device pointer

 * @speed: pointer to the speed of the link

 * @width: pointer to the width of the link

 *

 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the

 * AMD dGPU which may be a virtual upstream bridge.

 */

static void amdgpu_device_gpu_bandwidth(struct amdgpu_device *adev,

					enum pci_bus_speed *speed,

					enum pcie_link_width *width)

{

	struct pci_dev *parent = adev->pdev;



	if (!speed || !width)

		return;



	parent = pci_upstream_bridge(parent);

	if (parent && parent->vendor == PCI_VENDOR_ID_ATI) {

		/* use the upstream/downstream switches internal to dGPU */

		*speed = pcie_get_speed_cap(parent);

		*width = pcie_get_width_cap(parent);

		while ((parent = pci_upstream_bridge(parent))) {

			if (parent->vendor == PCI_VENDOR_ID_ATI) {

				/* use the upstream/downstream switches internal to dGPU */

				*speed = pcie_get_speed_cap(parent);

				*width = pcie_get_width_cap(parent);

			}

		}

	} else {

		/* use the device itself */

		*speed = pcie_get_speed_cap(adev->pdev);

		*width = pcie_get_width_cap(adev->pdev);

	}

}



/**

 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot

 *
@@ -6168,9 +6206,8 @@ static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev, 
 */

static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)

{

	struct pci_dev *pdev;

	enum pci_bus_speed speed_cap, platform_speed_cap;

	enum pcie_link_width platform_link_width;

	enum pcie_link_width platform_link_width, link_width;



	if (amdgpu_pcie_gen_cap)

		adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@@ -6192,11 +6229,10 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 


	amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,

					&platform_link_width);

	amdgpu_device_gpu_bandwidth(adev, &speed_cap, &link_width);



	if (adev->pm.pcie_gen_mask == 0) {

		/* asic caps */

		pdev = adev->pdev;

		speed_cap = pcie_get_speed_cap(pdev);

		if (speed_cap == PCI_SPEED_UNKNOWN) {

			adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |

						  CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
@@ -6252,12 +6288,64 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
		}

	}

	if (adev->pm.pcie_mlw_mask == 0) {

		/* asic caps */

		if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {

			adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK;

		} else {

			switch (link_width) {

			case PCIE_LNK_X32:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X16:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X12:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X8:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X4:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X2:

				adev->pm.pcie_mlw_mask |= (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X1:

				adev->pm.pcie_mlw_mask |= CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1;

				break;

			default:

				break;

			}

		}

		/* platform caps */

		if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {

			adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;

		} else {

			switch (platform_link_width) {

			case PCIE_LNK_X32:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
@@ -6266,7 +6354,7 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X16:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
@@ -6274,29 +6362,29 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) 
							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X12:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X8:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X4:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X2:

				adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |

				adev->pm.pcie_mlw_mask |= (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |

							   CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);

				break;

			case PCIE_LNK_X1:

				adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;

				adev->pm.pcie_mlw_mask |= CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;

				break;

			default:

				break;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+13 −13
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 
/**

 * DOC: gttsize (int)

 * Restrict the size of GTT domain (for userspace use) in MiB for testing.

 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).

 * The default is -1 (Use value specified by TTM).

 */

MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");

module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
@@ -399,7 +399,7 @@ module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 
 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).

 */

MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");

module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);

module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);



/**

 * DOC: bapm (int)
@@ -457,7 +457,7 @@ module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 
 * Enable experimental hw support (1 = enable). The default is 0 (disabled).

 */

MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");

module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);

module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444);



/**

 * DOC: dc (int)
@@ -568,14 +568,14 @@ module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 
 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).

 */

MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");

module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);

module_param_named_unsafe(gpu_recovery, amdgpu_gpu_recovery, int, 0444);



/**

 * DOC: emu_mode (int)

 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).

 */

MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");

module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);

module_param_named_unsafe(emu_mode, amdgpu_emu_mode, int, 0444);



/**

 * DOC: ras_enable (int)
@@ -730,7 +730,7 @@ module_param_named(noretry, amdgpu_noretry, int, 0644); 
 */

MODULE_PARM_DESC(force_asic_type,

	"A non negative value used to specify the asic type for all supported GPUs");

module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);

module_param_named_unsafe(force_asic_type, amdgpu_force_asic_type, int, 0444);



/**

 * DOC: use_xgmi_p2p (int)
@@ -749,7 +749,7 @@ module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 
 * assigns queues to HQDs.

 */

int sched_policy = KFD_SCHED_POLICY_HWS;

module_param(sched_policy, int, 0444);

module_param_unsafe(sched_policy, int, 0444);

MODULE_PARM_DESC(sched_policy,

	"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
@@ -799,7 +799,7 @@ MODULE_PARM_DESC(send_sigterm, 
 * Setting 1 enables halt on hang.

 */

int halt_if_hws_hang;

module_param(halt_if_hws_hang, int, 0644);

module_param_unsafe(halt_if_hws_hang, int, 0644);

MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");



/**
@@ -808,7 +808,7 @@ MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (defau 
 * check says. Default value: false (rely on MEC2 firmware version check).

 */

bool hws_gws_support;

module_param(hws_gws_support, bool, 0444);

module_param_unsafe(hws_gws_support, bool, 0444);

MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");



/**
@@ -841,7 +841,7 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa 
 */

int amdgpu_no_queue_eviction_on_vm_fault;

MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");

module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);

module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);

#endif



/**
@@ -849,7 +849,7 @@ module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm 
 */

int amdgpu_mtype_local;

MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");

module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);

module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444);



/**

 * DOC: pcie_p2p (bool)
@@ -953,7 +953,7 @@ module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 
 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)

 */

MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");

module_param_named(reset_method, amdgpu_reset_method, int, 0644);

module_param_named_unsafe(reset_method, amdgpu_reset_method, int, 0644);



/**

 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
@@ -1049,7 +1049,7 @@ module_param_named(seamless, amdgpu_seamless, int, 0444); 
 * - 0x4: Disable GPU soft recovery, always do a full reset

 */

MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");

module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);

module_param_named_unsafe(debug_mask, amdgpu_debug_mask, uint, 0444);



/**

 * DOC: agp (int)

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, 
	amdgpu_ring_patch_cond_exec(ring, cond_exec);



	ring->current_ctx = fence_ctx;

	if (vm && ring->funcs->emit_switch_buffer)

	if (job && ring->funcs->emit_switch_buffer)

		amdgpu_ring_emit_switch_buffer(ring);



	if (ring->funcs->emit_wave_limit &&

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+11 −8
Original line number Diff line number Diff line
@@ -846,7 +846,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
	case AMDGPU_INFO_DEV_INFO: {

		struct drm_amdgpu_info_device *dev_info;

		uint64_t vm_size;

		uint32_t pcie_gen_mask;

		uint32_t pcie_gen_mask, pcie_width_mask;



		dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);

		if (!dev_info)
@@ -934,15 +934,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;



		/* Combine the chip gen mask with the platform (CPU/mobo) mask. */

		pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);

		pcie_gen_mask = adev->pm.pcie_gen_mask &

			(adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);

		pcie_width_mask = adev->pm.pcie_mlw_mask &

			(adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);

		dev_info->pcie_gen = fls(pcie_gen_mask);

		dev_info->pcie_num_lanes =

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :

			adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :

			pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;



		dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;

		dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
#define AMDGPU_MES_VERSION_MASK		0x00000fff

#define AMDGPU_MES_API_VERSION_MASK	0x00fff000

#define AMDGPU_MES_FEAT_VERSION_MASK	0xff000000

#define AMDGPU_MES_MSCRATCH_SIZE	0x8000

#define AMDGPU_MES_MSCRATCH_SIZE	0x40000



enum amdgpu_mes_priority_level {

	AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,