Merge tag 'renesas-clk-for-v5.14-tag2' of... (7f8a37a4) · Commits · git / linux-net

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
		$schema: "http://devicetree.org/meta-schemas/core.yaml#"

		title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode

		maintainers:
		- Geert Uytterhoeven <geert+renesas@glider.be>

		description: \|
		On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
		Standby Mode share the same register block.

		They provide the following functionalities:
		- The CPG block generates various core clocks,
		- The Module Standby Mode block provides two functions:
		1. Module Standby, providing a Clock Domain to control the clock supply
		to individual SoC devices,
		2. Reset Control, to perform a software reset of individual SoC devices.

		properties:
		compatible:
		const: renesas,r9a07g044-cpg # RZ/G2{L,LC}

		reg:
		maxItems: 1

		clocks:
		maxItems: 1

		clock-names:
		description:
		Clock source to CPG can be either from external clock input (EXCLK) or
		crystal oscillator (XIN/XOUT).
		const: extal

		'#clock-cells':
		description: \|
		- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
		and a core clock reference, as defined in
		<dt-bindings/clock/r9a07g044-cpg.h>
		- For module clocks, the two clock specifier cells must be "CPG_MOD" and
		a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
		const: 2

		'#power-domain-cells':
		description:
		SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
		can be power-managed through Module Standby should refer to the CPG device
		node in their "power-domains" property, as documented by the generic PM
		Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
		const: 0

		'#reset-cells':
		description:
		The single reset specifier cell must be the module number, as defined in
		the <dt-bindings/clock/r9a07g044-cpg.h>.
		const: 1

		required:
		- compatible
		- reg
		- clocks
		- clock-names
		- '#clock-cells'
		- '#power-domain-cells'
		- '#reset-cells'

		additionalProperties: false

		examples:
		- \|
		cpg: clock-controller@11010000 {
		compatible = "renesas,r9a07g044-cpg";
		reg = <0x11010000 0x10000>;
		clocks = <&extal_clk>;
		clock-names = "extal";
		#clock-cells = <2>;
		#power-domain-cells = <0>;
		#reset-cells = <1>;
		};

drivers/clk/renesas/Kconfig

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		@@ -32,6 +32,7 @@ config CLK_RENESAS
		select CLK_R8A77995 if ARCH_R8A77995
		select CLK_R8A779A0 if ARCH_R8A779A0
		select CLK_R9A06G032 if ARCH_R9A06G032
		select CLK_R9A07G044 if ARCH_R9A07G044
		select CLK_SH73A0 if ARCH_SH73A0

		if CLK_RENESAS
		@@ -156,6 +157,10 @@ config CLK_R9A06G032
		help
		This is a driver for R9A06G032 clocks

		config CLK_R9A07G044
		bool "RZ/G2L clock support" if COMPILE_TEST
		select CLK_RZG2L

		config CLK_SH73A0
		bool "SH-Mobile AG5 clock support" if COMPILE_TEST
		select CLK_RENESAS_CPG_MSTP
		@@ -182,6 +187,10 @@ config CLK_RCAR_USB2_CLOCK_SEL
		help
		This is a driver for R-Car USB2 clock selector

		config CLK_RZG2L
		bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
		select RESET_CONTROLLER

		# Generic
		config CLK_RENESAS_CPG_MSSR
		bool "CPG/MSSR clock support" if COMPILE_TEST

drivers/clk/renesas/Makefile

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		@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
		obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
		obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
		obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
		obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
		obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o

		# Family
		@@ -36,6 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
		obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
		obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
		obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
		obj-$(CONFIG_CLK_RZG2L) += renesas-rzg2l-cpg.o

		# Generic
		obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o

drivers/clk/renesas/r9a07g044-cpg.c

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		// SPDX-License-Identifier: GPL-2.0
		/*
		* RZ/G2L CPG driver
		*
		* Copyright (C) 2021 Renesas Electronics Corp.
		*/

		#include <linux/clk-provider.h>
		#include <linux/device.h>
		#include <linux/init.h>
		#include <linux/kernel.h>

		#include <dt-bindings/clock/r9a07g044-cpg.h>

		#include "renesas-rzg2l-cpg.h"

		enum clk_ids {
		/* Core Clock Outputs exported to DT */
		LAST_DT_CORE_CLK = R9A07G044_OSCCLK,

		/* External Input Clocks */
		CLK_EXTAL,

		/* Internal Core Clocks */
		CLK_OSC_DIV1000,
		CLK_PLL1,
		CLK_PLL2,
		CLK_PLL2_DIV2,
		CLK_PLL2_DIV16,
		CLK_PLL2_DIV20,
		CLK_PLL3,
		CLK_PLL3_DIV2,
		CLK_PLL3_DIV4,
		CLK_PLL3_DIV8,
		CLK_PLL4,
		CLK_PLL5,
		CLK_PLL5_DIV2,
		CLK_PLL6,

		/* Module Clocks */
		MOD_CLK_BASE,
		};

		/* Divider tables */
		static const struct clk_div_table dtable_3b[] = {
		{0, 1},
		{1, 2},
		{2, 4},
		{3, 8},
		{4, 32},
		};

		static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
		/* External Clock Inputs */
		DEF_INPUT("extal", CLK_EXTAL),

		/* Internal Core Clocks */
		DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
		DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
		DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
		DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
		DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),

		DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
		DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
		DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),

		DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
		DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
		DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),

		/* Core output clk */
		DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
		DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
		dtable_3b, CLK_DIVIDER_HIWORD_MASK),
		DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
		DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
		DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
		};

		static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
		DEF_MOD("gic", R9A07G044_CLK_GIC600,
		R9A07G044_CLK_P1,
		0x514, BIT(0), (BIT(0) \| BIT(1))),
		DEF_MOD("ia55", R9A07G044_CLK_IA55,
		R9A07G044_CLK_P1,
		0x518, (BIT(0) \| BIT(1)), BIT(0)),
		DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
		R9A07G044_CLK_P0,
		0x584, BIT(0), BIT(0)),
		DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
		R9A07G044_CLK_P0,
		0x584, BIT(1), BIT(1)),
		DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
		R9A07G044_CLK_P0,
		0x584, BIT(2), BIT(2)),
		DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
		R9A07G044_CLK_P0,
		0x584, BIT(3), BIT(3)),
		DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
		R9A07G044_CLK_P0,
		0x584, BIT(4), BIT(4)),
		DEF_MOD("sci0", R9A07G044_CLK_SCI0,
		R9A07G044_CLK_P0,
		0x588, BIT(0), BIT(0)),
		};

		static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
		MOD_CLK_BASE + R9A07G044_CLK_GIC600,
		};

		const struct rzg2l_cpg_info r9a07g044_cpg_info = {
		/* Core Clocks */
		.core_clks = r9a07g044_core_clks,
		.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
		.last_dt_core_clk = LAST_DT_CORE_CLK,
		.num_total_core_clks = MOD_CLK_BASE,

		/* Critical Module Clocks */
		.crit_mod_clks = r9a07g044_crit_mod_clks,
		.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),

		/* Module Clocks */
		.mod_clks = r9a07g044_mod_clks,
		.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
		.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
		};

drivers/clk/renesas/renesas-rzg2l-cpg.c

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