Loading include/dt-bindings/clock/rockchip,rk3528-cru.h +6 −0 Original line number Diff line number Diff line Loading @@ -414,6 +414,12 @@ #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 #define MCLK_SDPDIF_SRC_PRE 404 #define SCLK_SDMMC_DRV 405 #define SCLK_SDMMC_SAMPLE 406 #define SCLK_SDIO0_DRV 407 #define SCLK_SDIO0_SAMPLE 408 #define SCLK_SDIO1_DRV 409 #define SCLK_SDIO1_SAMPLE 410 /* scmi-clocks indices */ #define SCMI_PCLK_KEYREADER 0 Loading include/dt-bindings/clock/rockchip,rk3576-cru.h +10 −0 Original line number Diff line number Diff line Loading @@ -594,4 +594,14 @@ #define SCMI_ARMCLK_B 11 #define SCMI_CLK_GPU 456 /* IOC-controlled output clocks */ #define CLK_SAI0_MCLKOUT_TO_IO 571 #define CLK_SAI1_MCLKOUT_TO_IO 572 #define CLK_SAI2_MCLKOUT_TO_IO 573 #define CLK_SAI3_MCLKOUT_TO_IO 574 #define CLK_SAI4_MCLKOUT_TO_IO 575 #define CLK_SAI4_MCLKOUT_TO_IO 575 #define CLK_FSPI0_TO_IO 576 #define CLK_FSPI1_TO_IO 577 #endif Loading
include/dt-bindings/clock/rockchip,rk3528-cru.h +6 −0 Original line number Diff line number Diff line Loading @@ -414,6 +414,12 @@ #define MCLK_I2S2_2CH_SAI_SRC_PRE 402 #define MCLK_I2S3_8CH_SAI_SRC_PRE 403 #define MCLK_SDPDIF_SRC_PRE 404 #define SCLK_SDMMC_DRV 405 #define SCLK_SDMMC_SAMPLE 406 #define SCLK_SDIO0_DRV 407 #define SCLK_SDIO0_SAMPLE 408 #define SCLK_SDIO1_DRV 409 #define SCLK_SDIO1_SAMPLE 410 /* scmi-clocks indices */ #define SCMI_PCLK_KEYREADER 0 Loading
include/dt-bindings/clock/rockchip,rk3576-cru.h +10 −0 Original line number Diff line number Diff line Loading @@ -594,4 +594,14 @@ #define SCMI_ARMCLK_B 11 #define SCMI_CLK_GPU 456 /* IOC-controlled output clocks */ #define CLK_SAI0_MCLKOUT_TO_IO 571 #define CLK_SAI1_MCLKOUT_TO_IO 572 #define CLK_SAI2_MCLKOUT_TO_IO 573 #define CLK_SAI3_MCLKOUT_TO_IO 574 #define CLK_SAI4_MCLKOUT_TO_IO 575 #define CLK_SAI4_MCLKOUT_TO_IO 575 #define CLK_FSPI0_TO_IO 576 #define CLK_FSPI1_TO_IO 577 #endif