Commit 80dc18a0 authored by Niklas Cassel's avatar Niklas Cassel Committed by Manivannan Sadhasivam
Browse files

PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up 



As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
training completes before sending a Configuration Request.

Add this delay in dw_pcie_wait_for_link(), after the link is reported as
up. The delay will only be performed in the success case where the link
came up.

DWC glue drivers that have a link up IRQ (drivers that set
use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they
perform this delay in their threaded link up IRQ handler.

Signed-off-by: default avatarNiklas Cassel <cassel@kernel.org>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Reviewed-by: default avatarWilfred Mallawa <wilfred.mallawa@wdc.com>
Link: https://patch.msgid.link/20250625102347.1205584-14-cassel@kernel.org
parent 15b6b243

drivers/pci/controller/dwc/pcie-designware.c

+8 −0
Original line number Diff line number Diff line
@@ -714,6 +714,14 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) 
		return -ETIMEDOUT;

	}



	/*

	 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link

	 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms

	 * after Link training completes before sending a Configuration Request.

	 */

	if (pci->max_link_speed > 2)

		msleep(PCIE_RESET_CONFIG_WAIT_MS);



	offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

	val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);