Commit 81557c96 authored by Relja Vojvodic's avatar Relja Vojvodic Committed by Alex Deucher
Browse files

drm/amd/display: Correct slice width calculation for YCbCr420 



[Why]
-OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to
incorrect slice width being calculated

[How]
-Ensure slice width is divisible by 2 for 420 to comply with spec

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarRelja Vojvodic <rvojvodi@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0975c4de

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

+1 −1
Original line number Diff line number Diff line
@@ -407,7 +407,7 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values 
	dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;



	// Need to find the ceiling value for the slice width

	dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h;

	dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h;

	// TODO: in addition to validating slice height (pic height must be divisible by slice height),

	// see what happens when the same condition doesn't apply for slice_width/pic_width.

	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ struct dsc_config { 
	enum dc_color_depth color_depth;  /* Bits per component */

	bool is_odm;

	struct dc_dsc_config dc_dsc_cfg;

	uint32_t dsc_padding;

};

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;



		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -1061,6 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;



		if (should_use_dto_dscclk)

			dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -364,6 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 
		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;

		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);

		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;

		dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;



		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);

		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);