Commit 830531e9 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/gsp/r535: add interrupt handling 



Fetches the interrupt table from RM, and hooks up the GSP interrupt
handler to message queue processing to catch async messages.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-36-skeggsb@gmail.com
parent 37e328a1

drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

+3 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ int nvkm_falcon_pio_rd(struct nvkm_falcon *, u8 port, enum nvkm_falcon_mem type, 
int nvkm_falcon_dma_wr(struct nvkm_falcon *, const u8 *img, u64 dma_addr, u32 dma_base,

		       enum nvkm_falcon_mem mem_type, u32 mem_base, int len, bool sec);

bool nvkm_falcon_riscv_active(struct nvkm_falcon *);

void nvkm_falcon_intr_retrigger(struct nvkm_falcon *);



int gm200_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);

int gm200_flcn_disable(struct nvkm_falcon *);
@@ -64,6 +65,8 @@ extern const struct nvkm_falcon_func_pio gp102_flcn_emem_pio; 


bool tu102_flcn_riscv_active(struct nvkm_falcon *);



void ga100_flcn_intr_retrigger(struct nvkm_falcon *);



int ga102_flcn_select(struct nvkm_falcon *);

int ga102_flcn_reset_prep(struct nvkm_falcon *);

int ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);

drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

+2 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ struct nvkm_falcon_func { 
	int (*enable)(struct nvkm_falcon *);

	int (*select)(struct nvkm_falcon *);

	u32 addr2;

	u32 riscv_irqmask;

	bool reset_pmc;

	int (*reset_eng)(struct nvkm_falcon *);

	int (*reset_prep)(struct nvkm_falcon *);
@@ -88,6 +89,7 @@ struct nvkm_falcon_func { 
	} cmdq, msgq;



	bool (*riscv_active)(struct nvkm_falcon *);

	void (*intr_retrigger)(struct nvkm_falcon *);



	struct {

		u32 *data;

drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h

+12 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ struct nvkm_gsp { 
			void *priv;

		} ntfy[16];

		int ntfy_nr;

		struct work_struct work;

	} msgq;



	bool running;
@@ -150,6 +151,14 @@ struct nvkm_gsp { 
		} device;

	} internal;



	struct {

		enum nvkm_subdev_type type;

		int inst;

		u32 stall;

		u32 nonstall;

	} intr[32];

	int intr_nr;



	const struct nvkm_gsp_rm {

		void *(*rpc_get)(struct nvkm_gsp *, u32 fn, u32 argc);

		void *(*rpc_push)(struct nvkm_gsp *, void *argv, bool wait, u32 repc);
@@ -378,6 +387,9 @@ nvkm_gsp_client_device_ctor(struct nvkm_gsp *gsp, 
	return ret;

}



int nvkm_gsp_intr_stall(struct nvkm_gsp *, enum nvkm_subdev_type, int);

int nvkm_gsp_intr_nonstall(struct nvkm_gsp *, enum nvkm_subdev_type, int);



int gv100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);

int tu102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);

int tu116_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h

0 → 100644
+62 −0
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__

#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 * SPDX-License-Identifier: MIT

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */



#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128



typedef enum NV2080_INTR_CATEGORY {

    NV2080_INTR_CATEGORY_DEFAULT = 0,

    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,

    NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,

    NV2080_INTR_CATEGORY_RUNLIST = 3,

    NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,

    NV2080_INTR_CATEGORY_UVM_OWNED = 5,

    NV2080_INTR_CATEGORY_UVM_SHARED = 6,

    NV2080_INTR_CATEGORY_ENUM_COUNT = 7,

} NV2080_INTR_CATEGORY;



typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {

    NvU8 subtreeStart;

    NvU8 subtreeEnd;

} NV2080_INTR_CATEGORY_SUBTREE_MAP;



typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {

    NvU16 engineIdx;

    NvU32 pmcIntrMask;

    NvU32 vectorStall;

    NvU32 vectorNonStall;

} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;



typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {

    NvU32                                            tableLen;

    NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];

    NV2080_INTR_CATEGORY_SUBTREE_MAP                 subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];

} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;



#endif

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
#ifndef __src_nvidia_inc_kernel_gpu_intr_engine_idx_h__

#define __src_nvidia_inc_kernel_gpu_intr_engine_idx_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

 * SPDX-License-Identifier: MIT

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */



#define MC_ENGINE_IDX_GSP                           49



#endif