Commit 83d78bbf authored by Kevin Brodsky's avatar Kevin Brodsky Committed by Catalin Marinas
Browse files

arm64/sysreg: Rename POE_RXW to POE_RWX 



It is customary to list R, W, X permissions in that order. In fact
this is already the case for PIE constants (PIE_RWX). Rename POE_RXW
accordingly, as well as POE_XW (currently unused).

While at it also swap the W/X lines in
compute_s1_overlay_permissions() to follow the R, W, X order.

Signed-off-by: default avatarKevin Brodsky <kevin.brodsky@arm.com>
Link: https://lore.kernel.org/r/20250219164029.2309119-3-kevin.brodsky@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent f91a3a60

arch/arm64/include/asm/sysreg.h

+3 −3
Original line number Diff line number Diff line
@@ -1077,8 +1077,8 @@ 
#define POE_RX		UL(0x3)

#define POE_W		UL(0x4)

#define POE_RW		UL(0x5)

#define POE_XW		UL(0x6)

#define POE_RXW		UL(0x7)

#define POE_WX		UL(0x6)

#define POE_RWX		UL(0x7)

#define POE_MASK	UL(0xf)



#define POR_ELx_BITS_PER_IDX		4
@@ -1087,7 +1087,7 @@ 
#define POR_ELx_PERM_PREP(idx, perm)	(((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))



/* Initial value for Permission Overlay Extension for EL0 */

#define POR_EL0_INIT	POE_RXW

#define POR_EL0_INIT	POE_RWX



/*

 * Definitions for Guarded Control Stack

arch/arm64/kernel/signal.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static void save_reset_user_access_state(struct user_access_state *ua_state) 
		u64 por_enable_all = 0;



		for (int pkey = 0; pkey < arch_max_pkey(); pkey++)

			por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RXW);

			por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RWX);



		ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0);

		write_sysreg_s(por_enable_all, SYS_POR_EL0);

arch/arm64/kvm/at.c

+4 −4
Original line number Diff line number Diff line
@@ -1090,22 +1090,22 @@ static void compute_s1_overlay_permissions(struct kvm_vcpu *vcpu, 
		break;

	}



	if (pov_perms & ~POE_RXW)

	if (pov_perms & ~POE_RWX)

		pov_perms = POE_NONE;



	if (wi->poe && wr->pov) {

		wr->pr &= pov_perms & POE_R;

		wr->px &= pov_perms & POE_X;

		wr->pw &= pov_perms & POE_W;

		wr->px &= pov_perms & POE_X;

	}



	if (uov_perms & ~POE_RXW)

	if (uov_perms & ~POE_RWX)

		uov_perms = POE_NONE;



	if (wi->e0poe && wr->uov) {

		wr->ur &= uov_perms & POE_R;

		wr->ux &= uov_perms & POE_X;

		wr->uw &= uov_perms & POE_W;

		wr->ux &= uov_perms & POE_X;

	}

}

arch/arm64/mm/mmu.c

+2 −2
Original line number Diff line number Diff line
@@ -1555,7 +1555,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp) 
#ifdef CONFIG_ARCH_HAS_PKEYS

int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned long init_val)

{

	u64 new_por = POE_RXW;

	u64 new_por;

	u64 old_por;



	if (!system_supports_poe())
@@ -1570,7 +1570,7 @@ int arch_set_user_pkey_access(struct task_struct *tsk, int pkey, unsigned long i 
		return -EINVAL;



	/* Set the bits we need in POR:  */

	new_por = POE_RXW;

	new_por = POE_RWX;

	if (init_val & PKEY_DISABLE_WRITE)

		new_por &= ~POE_W;

	if (init_val & PKEY_DISABLE_ACCESS)