Commit 83f6c3de authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.14-tag2' of... 

Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the RZ/G3E (R9A09G047) SoC
  - Add Module Stop (MSTOP) support on RZ/V2H
  - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
    R-Car V4H SoC
  - Add System Controller (SYS) reset and Generic Interrupt Controller
    (GIC) clock and reset entries on RZ/V2H

* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
  clk: renesas: r9a09g057: Add clock and reset entries for GIC
  clk: renesas: r9a09g057: Add reset entry for SYS
  clk: renesas: r8a779g0: Add VSPX clocks
  clk: renesas: r8a779g0: Add FCPVX clocks
  clk: renesas: r9a09g047: Add I2C clocks/resets
  clk: renesas: r9a09g047: Add CA55 core clocks
  clk: renesas: rzv2h: Add support for RZ/G3E SoC
  clk: renesas: rzv2h: Add MSTOP support
  dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
  dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
parents 39a72b4f e91609f1

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+9 −6
Original line number Diff line number Diff line
@@ -4,19 +4,22 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

    maxItems: 1
@@ -37,7 +40,7 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

+17 −0
Original line number Diff line number Diff line
@@ -525,6 +525,23 @@ properties: 
              - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0

          - const: renesas,r9a09g011



      - description: RZ/G3E (R9A09G047)

        items:

          - enum:

              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK

          - enum:

              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)

          - enum:

              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

drivers/clk/renesas/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ config CLK_RENESAS 
	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_R9A08G045 if ARCH_R9A08G045

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_R9A09G047 if ARCH_R9A09G047

	select CLK_R9A09G057 if ARCH_R9A09G057

	select CLK_SH73A0 if ARCH_SH73A0
@@ -194,6 +195,10 @@ config CLK_R9A09G011 
	bool "RZ/V2M clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A09G047

       bool "RZ/G3E clock support" if COMPILE_TEST

       select CLK_RZV2H



config CLK_R9A09G057

       bool "RZ/V2H(P) clock support" if COMPILE_TEST

       select CLK_RZV2H
@@ -234,7 +239,7 @@ config CLK_RZG2L 
	select RESET_CONTROLLER



config CLK_RZV2H

	bool "RZ/V2H(P) family clock support" if COMPILE_TEST

	bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



config CLK_RENESAS_VBATTB

drivers/clk/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o 
obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o

obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o

obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o

obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -238,6 +238,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),

	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),

	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),

	DEF_MOD("vspx0",	1028,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("vspx1",	1029,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D1_VIO),

	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),