Commit 8744df0e authored by Vikash Garodia's avatar Vikash Garodia Committed by Hans Verkuil
Browse files

media: iris: Add support for multiple clock sources 



vpu4 depends on more than one clock source. Thus far hardware versions
up to vpu3x have been clocked by a single source.
This adds support for multiple clocks by,
- Adding a lookup table
- Configuring OPP table for video device with different video clocks
- Setting OPP for multiple clocks during dev_pm_opp_set_opp()

This patch extends the support for multiple clocks in driver, which
would be used in subsequent patch for kaanapali, when the platform data
is prepared.

Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: default avatarVishnu Reddy <busanna.reddy@oss.qualcomm.com>
Signed-off-by: default avatarVishnu Reddy <busanna.reddy@oss.qualcomm.com>
Signed-off-by: default avatarVikash Garodia <vikash.garodia@oss.qualcomm.com>
Reviewed-by: default avatarDikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: default avatarBryan O'Donoghue <bod@kernel.org>
Signed-off-by: default avatarHans Verkuil <hverkuil+cisco@kernel.org>
parent 5ef0832c

drivers/media/platform/qcom/iris/iris_platform_common.h

+1 −0
Original line number Diff line number Diff line
@@ -221,6 +221,7 @@ struct iris_platform_data { 
	const char * const *opp_pd_tbl;

	unsigned int opp_pd_tbl_size;

	const struct platform_clk_data *clk_tbl;

	const char * const *opp_clk_tbl;

	unsigned int clk_tbl_size;

	const char * const *clk_rst_tbl;

	unsigned int clk_rst_tbl_size;

drivers/media/platform/qcom/iris/iris_platform_gen1.c

+7 −0
Original line number Diff line number Diff line
@@ -289,6 +289,11 @@ static const struct platform_clk_data sm8250_clk_table[] = { 
	{IRIS_HW_CLK,   "vcodec0_core" },

};



static const char * const sm8250_opp_clk_table[] = {

	"vcodec0_core",

	NULL,

};



static struct tz_cp_config tz_cp_config_sm8250 = {

	.cp_start = 0,

	.cp_size = 0x25800000,
@@ -349,6 +354,7 @@ const struct iris_platform_data sm8250_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),

	.clk_tbl = sm8250_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),

	.opp_clk_tbl = sm8250_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu-1.0/venus.mbn",
@@ -400,6 +406,7 @@ const struct iris_platform_data sc7280_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),

	.clk_tbl = sc7280_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),

	.opp_clk_tbl = sc7280_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu20_p1.mbn",

drivers/media/platform/qcom/iris/iris_platform_gen2.c

+9 −0
Original line number Diff line number Diff line
@@ -785,6 +785,11 @@ static const struct platform_clk_data sm8550_clk_table[] = { 
	{IRIS_HW_CLK,   "vcodec0_core" },

};



static const char * const sm8550_opp_clk_table[] = {

	"vcodec0_core",

	NULL,

};



static struct ubwc_config_data ubwc_config_sm8550 = {

	.max_channels = 8,

	.mal_length = 32,
@@ -933,6 +938,7 @@ const struct iris_platform_data sm8550_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),

	.clk_tbl = sm8550_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),

	.opp_clk_tbl = sm8550_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu30_p4.mbn",
@@ -1036,6 +1042,7 @@ const struct iris_platform_data sm8650_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),

	.clk_tbl = sm8550_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),

	.opp_clk_tbl = sm8550_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu33_p4.mbn",
@@ -1130,6 +1137,7 @@ const struct iris_platform_data sm8750_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),

	.clk_tbl = sm8750_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),

	.opp_clk_tbl = sm8550_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu35_p4.mbn",
@@ -1228,6 +1236,7 @@ const struct iris_platform_data qcs8300_data = { 
	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),

	.clk_tbl = sm8550_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),

	.opp_clk_tbl = sm8550_opp_clk_table,

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu30_p4_s6.mbn",

drivers/media/platform/qcom/iris/iris_platform_sc7280.h

+5 −0
Original line number Diff line number Diff line
@@ -23,4 +23,9 @@ static const struct platform_clk_data sc7280_clk_table[] = { 
	{IRIS_HW_AHB_CLK,  "vcodec_bus"   },

};



static const char * const sc7280_opp_clk_table[] = {

	"vcodec_core",

	NULL,

};



#endif

drivers/media/platform/qcom/iris/iris_power.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static int iris_set_clocks(struct iris_inst *inst) 
	}



	core->power.clk_freq = freq;

	ret = dev_pm_opp_set_rate(core->dev, freq);

	ret = iris_opp_set_rate(core->dev, freq);

	mutex_unlock(&core->lock);



	return ret;