Commit 87cfc79d authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Resolve the meaning of UBWC_MODE 



This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".

This commit is intentionally cross-subsystem to ease review, as the
patchset is intended to be merged together, with a maintainer
consensus.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660971/


Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 32ef24e5

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -687,11 +687,11 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
	 */

	BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);

	u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;

	bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);

	bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;

	u8 uavflagprd_inv = 0;

	u32 hbb_hi = hbb >> 2;

	u32 hbb_lo = hbb & 3;

	u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;

	u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);



	if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))

include/linux/soc/qcom/ubwc.h

+10 −0
Original line number Diff line number Diff line
@@ -62,4 +62,14 @@ static inline const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void) 
}

#endif



static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)

{

	bool ret = cfg->ubwc_enc_version == UBWC_1_0;



	if (ret && !(cfg->ubwc_swizzle & BIT(0)))

		pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");



	return ret;

}



#endif /* __QCOM_UBWC_H__ */