Unverified Commit 88139af7 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Rodrigo Vivi
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drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake 



At the moment the driver does not support AuxCCS at all due respective
modifiers being hidden from userspace.

As we are about to start enabling them, starting with Alderlake, let us
begin by limiting the ring buffer support to just that initial platform.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260324084018.20353-4-tvrtko.ursulin@igalia.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 36052e56

drivers/gpu/drm/xe/xe_ring_ops.c

+2 −2
Original line number Diff line number Diff line
@@ -334,9 +334,9 @@ static bool has_aux_ccs(struct xe_device *xe) 
	 * PVC is a special case that has no compression of either type

	 * (FlatCCS or AuxCCS).  Also, AuxCCS is no longer used from Xe2

	 * onward, so any future platforms with no FlatCCS will not have

	 * AuxCCS either.

	 * AuxCCS, and we explicitly do not want to support it on MTL.

	 */

	if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)

	if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC)

		return false;



	return !xe->info.has_flat_ccs;