Commit 885b92ba authored by Andy Shevchenko's avatar Andy Shevchenko
Browse files

Merge patch series "pinctrl: intel: Convert the rest to use INTEL_GPP()" 

Andy Shevchenko <andriy.shevchenko@linux.intel.com> says:

A few drivers use the more customised versions of INTEL_GPP().
Convert them to use INTEL_GPP() directly.

Link: https://patch.msgid.link/20251111191214.1378051-1-andriy.shevchenko@linux.intel.com


Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
parents 396f45a3 cc4e46fa

drivers/pinctrl/intel/pinctrl-cedarfork.c

+15 −22
Original line number Diff line number Diff line
@@ -21,13 +21,6 @@ 
#define CDF_GPI_IS	0x200

#define CDF_GPI_IE	0x230



#define CDF_GPP(r, s, e)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

	}



#define CDF_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
@@ -288,24 +281,24 @@ static const struct pinctrl_pin_desc cdf_pins[] = { 
};



static const struct intel_padgroup cdf_community0_gpps[] = {

	CDF_GPP(0, 0, 23),	/* WEST2 */

	CDF_GPP(1, 24, 47),	/* WEST3 */

	CDF_GPP(2, 48, 70),	/* WEST01 */

	CDF_GPP(3, 71, 90),	/* WEST5 */

	CDF_GPP(4, 91, 96),	/* WESTC */

	CDF_GPP(5, 97, 101),	/* WESTC_DFX */

	CDF_GPP(6, 102, 111),	/* WESTA */

	CDF_GPP(7, 112, 123),	/* WESTB */

	CDF_GPP(8, 124, 143),	/* WESTD */

	CDF_GPP(9, 144, 144),	/* WESTD_PECI */

	CDF_GPP(10, 145, 167),	/* WESTF */

	INTEL_GPP(0, 0, 23, 0),		/* WEST2 */

	INTEL_GPP(1, 24, 47, 24),	/* WEST3 */

	INTEL_GPP(2, 48, 70, 48),	/* WEST01 */

	INTEL_GPP(3, 71, 90, 71),	/* WEST5 */

	INTEL_GPP(4, 91, 96, 91),	/* WESTC */

	INTEL_GPP(5, 97, 101, 97),	/* WESTC_DFX */

	INTEL_GPP(6, 102, 111, 102),	/* WESTA */

	INTEL_GPP(7, 112, 123, 112),	/* WESTB */

	INTEL_GPP(8, 124, 143, 124),	/* WESTD */

	INTEL_GPP(9, 144, 144, 144),	/* WESTD_PECI */

	INTEL_GPP(10, 145, 167, 145),	/* WESTF */

};



static const struct intel_padgroup cdf_community1_gpps[] = {

	CDF_GPP(0, 168, 191),	/* EAST2 */

	CDF_GPP(1, 192, 202),	/* EAST3 */

	CDF_GPP(2, 203, 225),	/* EAST0 */

	CDF_GPP(3, 226, 236),	/* EMMC */

	INTEL_GPP(0, 168, 191, 168),	/* EAST2 */

	INTEL_GPP(1, 192, 202, 192),	/* EAST3 */

	INTEL_GPP(2, 203, 225, 203),	/* EAST0 */

	INTEL_GPP(3, 226, 236, 226),	/* EMMC */

};



static const struct intel_community cdf_communities[] = {

drivers/pinctrl/intel/pinctrl-cherryview.c

+20 −26
Original line number Diff line number Diff line
@@ -92,12 +92,6 @@ struct intel_community_context { 


#define PINMODE(m, i)		((m) | ((i) * PINMODE_INVERT_OE))



#define CHV_GPP(start, end)			\

	{					\

		.base = (start),		\

		.size = (end) - (start) + 1,	\

	}



#define CHV_COMMUNITY(g, i, a)			\

	{					\

		.gpps = (g),			\
@@ -258,13 +252,13 @@ static const struct intel_function southwest_functions[] = { 
};



static const struct intel_padgroup southwest_gpps[] = {

	CHV_GPP(0, 7),

	CHV_GPP(15, 22),

	CHV_GPP(30, 37),

	CHV_GPP(45, 52),

	CHV_GPP(60, 67),

	CHV_GPP(75, 82),

	CHV_GPP(90, 97),

	INTEL_GPP(0, 0, 7, 0),

	INTEL_GPP(1, 15, 22, 15),

	INTEL_GPP(2, 30, 37, 30),

	INTEL_GPP(3, 45, 52, 45),

	INTEL_GPP(4, 60, 67, 60),

	INTEL_GPP(5, 75, 82, 75),

	INTEL_GPP(6, 90, 97, 90),

};



/*
@@ -354,11 +348,11 @@ static const struct pinctrl_pin_desc north_pins[] = { 
};



static const struct intel_padgroup north_gpps[] = {

	CHV_GPP(0, 8),

	CHV_GPP(15, 27),

	CHV_GPP(30, 41),

	CHV_GPP(45, 56),

	CHV_GPP(60, 72),

	INTEL_GPP(0, 0, 8, 0),

	INTEL_GPP(1, 15, 27, 15),

	INTEL_GPP(2, 30, 41, 30),

	INTEL_GPP(3, 45, 56, 45),

	INTEL_GPP(4, 60, 72, 60),

};



/*
@@ -406,8 +400,8 @@ static const struct pinctrl_pin_desc east_pins[] = { 
};



static const struct intel_padgroup east_gpps[] = {

	CHV_GPP(0, 11),

	CHV_GPP(15, 26),

	INTEL_GPP(0, 0, 11, 0),

	INTEL_GPP(1, 15, 26, 15),

};



static const struct intel_community east_communities[] = {
@@ -526,12 +520,12 @@ static const struct intel_function southeast_functions[] = { 
};



static const struct intel_padgroup southeast_gpps[] = {

	CHV_GPP(0, 7),

	CHV_GPP(15, 26),

	CHV_GPP(30, 35),

	CHV_GPP(45, 52),

	CHV_GPP(60, 69),

	CHV_GPP(75, 85),

	INTEL_GPP(0, 0, 7, 0),

	INTEL_GPP(1, 15, 26, 15),

	INTEL_GPP(2, 30, 35, 30),

	INTEL_GPP(3, 45, 52, 45),

	INTEL_GPP(4, 60, 69, 60),

	INTEL_GPP(5, 75, 85, 75),

};



static const struct intel_community southeast_communities[] = {

drivers/pinctrl/intel/pinctrl-denverton.c

+7 −14
Original line number Diff line number Diff line
@@ -21,13 +21,6 @@ 
#define DNV_GPI_IS	0x100

#define DNV_GPI_IE	0x120



#define DNV_GPP(n, s, e)				\

	{						\

		.reg_num = (n),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

	}



#define DNV_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
@@ -222,16 +215,16 @@ static const struct intel_function dnv_functions[] = { 
};



static const struct intel_padgroup dnv_north_gpps[] = {

	DNV_GPP(0, 0, 31),	/* North ALL_0 */

	DNV_GPP(1, 32, 40),	/* North ALL_1 */

	INTEL_GPP(0, 0, 31, 0),		/* North ALL_0 */

	INTEL_GPP(1, 32, 40, 32),	/* North ALL_1 */

};



static const struct intel_padgroup dnv_south_gpps[] = {

	DNV_GPP(0, 41, 58),	/* South DFX */

	DNV_GPP(1, 59, 90),	/* South GPP0_0 */

	DNV_GPP(2, 91, 111),	/* South GPP0_1 */

	DNV_GPP(3, 112, 143),	/* South GPP1_0 */

	DNV_GPP(4, 144, 153),	/* South GPP1_1 */

	INTEL_GPP(0, 41, 58, 41),	/* South DFX */

	INTEL_GPP(1, 59, 90, 59),	/* South GPP0_0 */

	INTEL_GPP(2, 91, 111, 91),	/* South GPP0_1 */

	INTEL_GPP(3, 112, 143, 112),	/* South GPP1_0 */

	INTEL_GPP(4, 144, 153, 144),	/* South GPP1_1 */

};



static const struct intel_community dnv_communities[] = {

drivers/pinctrl/intel/pinctrl-elkhartlake.c

+18 −25
Original line number Diff line number Diff line
@@ -21,13 +21,6 @@ 
#define EHL_GPI_IS	0x100

#define EHL_GPI_IE	0x120



#define EHL_GPP(r, s, e)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

	}



#define EHL_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
@@ -106,9 +99,9 @@ static const struct pinctrl_pin_desc ehl_community0_pins[] = { 
};



static const struct intel_padgroup ehl_community0_gpps[] = {

	EHL_GPP(0, 0, 25),	/* GPP_B */

	EHL_GPP(1, 26, 41),	/* GPP_T */

	EHL_GPP(2, 42, 66),	/* GPP_G */

	INTEL_GPP(0, 0, 25, 0),		/* GPP_B */

	INTEL_GPP(1, 26, 41, 26),	/* GPP_T */

	INTEL_GPP(2, 42, 66, 42),	/* GPP_G */

};



static const struct intel_community ehl_community0[] = {
@@ -245,11 +238,11 @@ static const struct pinctrl_pin_desc ehl_community1_pins[] = { 
};



static const struct intel_padgroup ehl_community1_gpps[] = {

	EHL_GPP(0, 0, 15),	/* GPP_V */

	EHL_GPP(1, 16, 39),	/* GPP_H */

	EHL_GPP(2, 40, 60),	/* GPP_D */

	EHL_GPP(3, 61, 84),	/* GPP_U */

	EHL_GPP(4, 85, 112),	/* vGPIO */

	INTEL_GPP(0, 0, 15, 0),		/* GPP_V */

	INTEL_GPP(1, 16, 39, 16),	/* GPP_H */

	INTEL_GPP(2, 40, 60, 40),	/* GPP_D */

	INTEL_GPP(3, 61, 84, 61),	/* GPP_U */

	INTEL_GPP(4, 85, 112, 85),	/* vGPIO */

};



static const struct intel_community ehl_community1[] = {
@@ -286,7 +279,7 @@ static const struct pinctrl_pin_desc ehl_community2_pins[] = { 
};



static const struct intel_padgroup ehl_community2_gpps[] = {

	EHL_GPP(0, 0, 16),	/* DSW */

	INTEL_GPP(0, 0, 16, 0),		/* DSW */

};



static const struct intel_community ehl_community2[] = {
@@ -356,10 +349,10 @@ static const struct pinctrl_pin_desc ehl_community3_pins[] = { 
};



static const struct intel_padgroup ehl_community3_gpps[] = {

	EHL_GPP(0, 0, 16),	/* CPU */

	EHL_GPP(1, 17, 18),	/* GPP_S */

	EHL_GPP(2, 19, 42),	/* GPP_A */

	EHL_GPP(3, 43, 46),	/* vGPIO_3 */

	INTEL_GPP(0, 0, 16,  0),	/* CPU */

	INTEL_GPP(1, 17, 18, 17),	/* GPP_S */

	INTEL_GPP(2, 19, 42, 19),	/* GPP_A */

	INTEL_GPP(3, 43, 46, 43),	/* vGPIO_3 */

};



static const struct intel_community ehl_community3[] = {
@@ -462,10 +455,10 @@ static const struct pinctrl_pin_desc ehl_community4_pins[] = { 
};



static const struct intel_padgroup ehl_community4_gpps[] = {

	EHL_GPP(0, 0, 23),	/* GPP_C */

	EHL_GPP(1, 24, 48),	/* GPP_F */

	EHL_GPP(2, 49, 54),	/* HVCMOS */

	EHL_GPP(3, 55, 79),	/* GPP_E */

	INTEL_GPP(0, 0, 23, 0),		/* GPP_C */

	INTEL_GPP(1, 24, 48, 24),	/* GPP_F */

	INTEL_GPP(2, 49, 54, 49),	/* HVCMOS */

	INTEL_GPP(3, 55, 79, 55),	/* GPP_E */

};



static const struct intel_community ehl_community4[] = {
@@ -493,7 +486,7 @@ static const struct pinctrl_pin_desc ehl_community5_pins[] = { 
};



static const struct intel_padgroup ehl_community5_gpps[] = {

	EHL_GPP(0, 0, 7),	/* GPP_R */

	INTEL_GPP(0, 0, 7, 0),		/* GPP_R */

};



static const struct intel_community ehl_community5[] = {

drivers/pinctrl/intel/pinctrl-emmitsburg.c

+13 −20
Original line number Diff line number Diff line
@@ -21,13 +21,6 @@ 
#define EBG_GPI_IS	0x200

#define EBG_GPI_IE	0x210



#define EBG_GPP(r, s, e)				\

	{						\

		.reg_num = (r),				\

		.base = (s),				\

		.size = ((e) - (s) + 1),		\

	}



#define EBG_COMMUNITY(b, s, e, g)			\

	INTEL_COMMUNITY_GPPS(b, s, e, g, EBG)
@@ -311,31 +304,31 @@ static const struct pinctrl_pin_desc ebg_pins[] = { 
};



static const struct intel_padgroup ebg_community0_gpps[] = {

	EBG_GPP(0, 0, 20),	/* GPP_A */

	EBG_GPP(1, 21, 44),	/* GPP_B */

	EBG_GPP(2, 45, 65),	/* SPI */

	INTEL_GPP(0, 0, 20, 0),		/* GPP_A */

	INTEL_GPP(1, 21, 44, 21),	/* GPP_B */

	INTEL_GPP(2, 45, 65, 45),	/* SPI */

};



static const struct intel_padgroup ebg_community1_gpps[] = {

	EBG_GPP(0, 66, 87),	/* GPP_C */

	EBG_GPP(1, 88, 111),	/* GPP_D */

	INTEL_GPP(0, 66, 87, 66),	/* GPP_C */

	INTEL_GPP(1, 88, 111, 88),	/* GPP_D */

};



static const struct intel_padgroup ebg_community3_gpps[] = {

	EBG_GPP(0, 112, 135),	/* GPP_E */

	EBG_GPP(1, 136, 145),	/* JTAG */

	INTEL_GPP(0, 112, 135, 112),	/* GPP_E */

	INTEL_GPP(1, 136, 145, 136),	/* JTAG */

};



static const struct intel_padgroup ebg_community4_gpps[] = {

	EBG_GPP(0, 146, 165),	/* GPP_H */

	EBG_GPP(1, 166, 183),	/* GPP_J */

	INTEL_GPP(0, 146, 165, 146),	/* GPP_H */

	INTEL_GPP(1, 166, 183, 166),	/* GPP_J */

};



static const struct intel_padgroup ebg_community5_gpps[] = {

	EBG_GPP(0, 184, 207),	/* GPP_I */

	EBG_GPP(1, 208, 225),	/* GPP_L */

	EBG_GPP(2, 226, 243),	/* GPP_M */

	EBG_GPP(3, 244, 261),	/* GPP_N */

	INTEL_GPP(0, 184, 207, 184),	/* GPP_I */

	INTEL_GPP(1, 208, 225, 208),	/* GPP_L */

	INTEL_GPP(2, 226, 243, 226),	/* GPP_M */

	INTEL_GPP(3, 244, 261, 244),	/* GPP_N */

};



static const struct intel_community ebg_communities[] = {