Commit 89571d7c authored by Mauro Rossi's avatar Mauro Rossi Committed by Alex Deucher
Browse files

drm/amd/display: dce_ipp: add DCE6 specific macros,functions 



[Why]
DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL register

[How]
Add DCE6 specific macros definitions for IPP masks
DCE6 IPP macros will avoid buiding errors when using DCE6 headers
Add dce60_ipp_set_degamma() function w/o Cursor2 Degamma programming
Use dce60_ipp_set_degamma() in ipp_funcs dce60_ipp_funcs
Add DCE6 specific dce60_ipp_construct

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMauro Rossi <issor.oruam@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ff0649f8

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

+46 −0
Original line number Diff line number Diff line
@@ -231,6 +231,22 @@ static void dce_ipp_set_degamma( 
		  CURSOR2_DEGAMMA_MODE, degamma_type);

}



#if defined(CONFIG_DRM_AMD_DC_SI)

static void dce60_ipp_set_degamma(

	struct input_pixel_processor *ipp,

	enum ipp_degamma_mode mode)

{

	struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);

	uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;



	ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);

	/* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */

	REG_SET_2(DEGAMMA_CONTROL, 0,

		  GRPH_DEGAMMA_MODE, degamma_type,

		  CURSOR_DEGAMMA_MODE, degamma_type);

}

#endif



static const struct ipp_funcs dce_ipp_funcs = {

	.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,

	.ipp_cursor_set_position = dce_ipp_cursor_set_position,
@@ -239,6 +255,17 @@ static const struct ipp_funcs dce_ipp_funcs = { 
	.ipp_set_degamma = dce_ipp_set_degamma

};



#if defined(CONFIG_DRM_AMD_DC_SI)

static const struct ipp_funcs dce60_ipp_funcs = {

	.ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,

	.ipp_cursor_set_position = dce_ipp_cursor_set_position,

	.ipp_program_prescale = dce_ipp_program_prescale,

	.ipp_program_input_lut = dce_ipp_program_input_lut,

	.ipp_set_degamma = dce60_ipp_set_degamma

};

#endif





/*****************************************/

/* Constructor, Destructor               */

/*****************************************/
@@ -260,6 +287,25 @@ void dce_ipp_construct( 
	ipp_dce->ipp_mask = ipp_mask;

}



#if defined(CONFIG_DRM_AMD_DC_SI)

void dce60_ipp_construct(

	struct dce_ipp *ipp_dce,

	struct dc_context *ctx,

	int inst,

	const struct dce_ipp_registers *regs,

	const struct dce_ipp_shift *ipp_shift,

	const struct dce_ipp_mask *ipp_mask)

{

	ipp_dce->base.ctx = ctx;

	ipp_dce->base.inst = inst;

	ipp_dce->base.funcs = &dce60_ipp_funcs;



	ipp_dce->regs = regs;

	ipp_dce->ipp_shift = ipp_shift;

	ipp_dce->ipp_mask = ipp_mask;

}

#endif



void dce_ipp_destroy(struct input_pixel_processor **ipp)

{

	kfree(TO_DCE_IPP(*ipp));

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

+49 −0
Original line number Diff line number Diff line
@@ -147,6 +147,46 @@ 
	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \

	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_SI)

#define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \

	IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \

	IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \

	IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \

	IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \

	IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \

	IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \

	IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \

	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \

	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \

	IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \

	IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \

	IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \

	IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \

	IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \

	IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \

	IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \

	IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \

	IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \

	IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \

	IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \

	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \

	IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \

	IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \

	IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \

	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \

	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \

	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \

	IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \

	IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \

	IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \

	IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh)

#endif



#define IPP_REG_FIELD_LIST(type) \

	type CURSOR_UPDATE_LOCK; \

	type CURSOR_EN; \
@@ -233,6 +273,15 @@ void dce_ipp_construct(struct dce_ipp *ipp_dce, 
	const struct dce_ipp_shift *ipp_shift,

	const struct dce_ipp_mask *ipp_mask);



#if defined(CONFIG_DRM_AMD_DC_SI)

void dce60_ipp_construct(struct dce_ipp *ipp_dce,

	struct dc_context *ctx,

	int inst,

	const struct dce_ipp_registers *regs,

	const struct dce_ipp_shift *ipp_shift,

	const struct dce_ipp_mask *ipp_mask);

#endif



void dce_ipp_destroy(struct input_pixel_processor **ipp);



#endif /* _DCE_IPP_H_ */