Commit 89b85751 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: pass dev_priv explicitly to DSPSURFLIVE 



Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURFLIVE register macro.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bc252dee67718f729883da7d542c6435384683ae.1716469091.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 495d6f77

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ 
#define DSPOFFSET(dev_priv, plane)		_MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)



#define _DSPASURFLIVE				0x701AC /* g4x+ */

#define DSPSURFLIVE(plane)			_MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)

#define DSPSURFLIVE(dev_priv, plane)		_MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)



#define _DSPAGAMC				0x701E0 /* pre-g4x */

#define DSPGAMC(plane, i)			_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */

drivers/gpu/drm/i915/gvt/handlers.c

+2 −2
Original line number Diff line number Diff line
@@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
	int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);



	write_vreg(vgpu, offset, p_data, bytes);

	vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

	vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);



	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
@@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu, 


	write_vreg(vgpu, offset, p_data, bytes);

	if (plane == PLANE_PRIMARY) {

		vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

		vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);

		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

	} else {

		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

+3 −3
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) 
	MMIO_D(DSPSIZE(dev_priv, PIPE_A));

	MMIO_D(DSPSURF(dev_priv, PIPE_A));

	MMIO_D(DSPOFFSET(dev_priv, PIPE_A));

	MMIO_D(DSPSURFLIVE(PIPE_A));

	MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));

	MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));

	MMIO_D(DSPCNTR(dev_priv, PIPE_B));

	MMIO_D(DSPADDR(dev_priv, PIPE_B));
@@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) 
	MMIO_D(DSPSIZE(dev_priv, PIPE_B));

	MMIO_D(DSPSURF(dev_priv, PIPE_B));

	MMIO_D(DSPOFFSET(dev_priv, PIPE_B));

	MMIO_D(DSPSURFLIVE(PIPE_B));

	MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));

	MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));

	MMIO_D(DSPCNTR(dev_priv, PIPE_C));

	MMIO_D(DSPADDR(dev_priv, PIPE_C));
@@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) 
	MMIO_D(DSPSIZE(dev_priv, PIPE_C));

	MMIO_D(DSPSURF(dev_priv, PIPE_C));

	MMIO_D(DSPOFFSET(dev_priv, PIPE_C));

	MMIO_D(DSPSURFLIVE(PIPE_C));

	MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));

	MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));

	MMIO_D(SPRCTL(PIPE_A));

	MMIO_D(SPRLINOFF(PIPE_A));