Commit 8a6dcb26 authored by Ian Rogers's avatar Ian Rogers Committed by Namhyung Kim
Browse files

perf vendor events: Update Tigerlake events/metrics 

Update events from v1.16 to v1.17.
Update TMA metrics from 4.8 to 5.02.

Bring in the event updates v1.17:
https://github.com/intel/perfmon/commit/e1d5ac3412450bf049301cb26206d03c41066b83

The TMA 5.02 addition is from (with subsequent fixes):
https://github.com/intel/perfmon/commit/1d72913b2d938781fb28f3cc3507aaec5c22d782



Co-developed-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Signed-off-by: default avatarCaleb Biggers <caleb.biggers@intel.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Tested-by: default avatarThomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250211213031.114209-24-irogers@google.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent f2f3a4af

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core 
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core

GenuineIntel-6-55-[01234],v1.36,skylakex,core

GenuineIntel-6-86,v1.23,snowridgex,core

GenuineIntel-6-8[CD],v1.16,tigerlake,core

GenuineIntel-6-8[CD],v1.17,tigerlake,core

GenuineIntel-6-2C,v5,westmereep-dp,core

GenuineIntel-6-25,v4,westmereep-sp,core

GenuineIntel-6-2F,v4,westmereex,core

tools/perf/pmu-events/arch/x86/tigerlake/cache.json

+22 −23
Original line number Diff line number Diff line
@@ -75,14 +75,23 @@ 
        "UMask": "0x2"

    },

    {

        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",

        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",

        "Counter": "0,1,2,3",

        "EventCode": "0xf2",

        "EventName": "L2_LINES_OUT.SILENT",

        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",

        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",

        "Counter": "0,1,2,3",

        "EventCode": "0xf2",

        "EventName": "L2_LINES_OUT.USELESS_HWPF",

        "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "L2 code requests",

        "Counter": "0,1,2,3",
@@ -233,7 +242,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",

        "SampleAfterValue": "1000003",

        "UMask": "0x81"
@@ -244,7 +252,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ALL_STORES",

        "PEBS": "1",

        "PublicDescription": "Counts all retired store instructions.",

        "SampleAfterValue": "1000003",

        "UMask": "0x82"
@@ -255,7 +262,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.ANY",

        "PEBS": "1",

        "PublicDescription": "Counts all retired memory instructions - loads and stores.",

        "SampleAfterValue": "1000003",

        "UMask": "0x83"
@@ -266,7 +272,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with locked access.",

        "SampleAfterValue": "100007",

        "UMask": "0x21"
@@ -277,7 +282,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",

        "SampleAfterValue": "100003",

        "UMask": "0x41"
@@ -288,7 +292,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",

        "PEBS": "1",

        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",

        "SampleAfterValue": "100003",

        "UMask": "0x42"
@@ -299,7 +302,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",

        "PEBS": "1",

        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",

        "SampleAfterValue": "100003",

        "UMask": "0x11"
@@ -310,7 +312,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",

        "PEBS": "1",

        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",

        "SampleAfterValue": "100003",

        "UMask": "0x12"
@@ -321,7 +322,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd2",

        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",

        "SampleAfterValue": "20011",

        "UMask": "0x4"
@@ -332,7 +332,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd2",

        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",

        "PEBS": "1",

        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",

        "SampleAfterValue": "20011",

        "UMask": "0x1"
@@ -343,7 +342,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd2",

        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",

        "SampleAfterValue": "100003",

        "UMask": "0x8"
@@ -354,7 +352,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd2",

        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",

        "SampleAfterValue": "20011",

        "UMask": "0x2"
@@ -365,7 +362,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd4",

        "EventName": "MEM_LOAD_MISC_RETIRED.UC",

        "PEBS": "1",

        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access",

        "SampleAfterValue": "100007",

        "UMask": "0x4"
@@ -376,7 +372,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.FB_HIT",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",

        "SampleAfterValue": "100007",

        "UMask": "0x40"
@@ -387,7 +382,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L1_HIT",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",

        "SampleAfterValue": "1000003",

        "UMask": "0x1"
@@ -398,7 +392,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L1_MISS",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",

        "SampleAfterValue": "200003",

        "UMask": "0x8"
@@ -409,7 +402,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L2_HIT",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"
@@ -420,7 +412,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L2_MISS",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",

        "SampleAfterValue": "100021",

        "UMask": "0x10"
@@ -431,7 +422,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L3_HIT",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",

        "SampleAfterValue": "100021",

        "UMask": "0x4"
@@ -442,7 +432,6 @@ 
        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_RETIRED.L3_MISS",

        "PEBS": "1",

        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",

        "SampleAfterValue": "50021",

        "UMask": "0x20"
@@ -458,7 +447,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",

        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the data to the requesting core.",

        "Counter": "0,1,2,3",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
@@ -532,6 +521,16 @@ 
        "SampleAfterValue": "1000003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",

        "Counter": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0x60",

        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",

        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",

        "SampleAfterValue": "1000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/tigerlake/frontend.json

+0 −17
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ 
        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x1",

        "PEBS": "1",

        "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -56,7 +55,6 @@ 
        "EventName": "FRONTEND_RETIRED.DSB_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x11",

        "PEBS": "1",

        "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -68,7 +66,6 @@ 
        "EventName": "FRONTEND_RETIRED.ITLB_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x14",

        "PEBS": "1",

        "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -80,7 +77,6 @@ 
        "EventName": "FRONTEND_RETIRED.L1I_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x12",

        "PEBS": "1",

        "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -92,7 +88,6 @@ 
        "EventName": "FRONTEND_RETIRED.L2_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x13",

        "PEBS": "1",

        "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -104,7 +99,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x500106",

        "PEBS": "1",

        "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -116,7 +110,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x508006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -128,7 +121,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x501006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -140,7 +132,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x500206",

        "PEBS": "1",

        "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -152,7 +143,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x510006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -164,7 +154,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x100206",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -176,7 +165,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x502006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -188,7 +176,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x500406",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -200,7 +187,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x520006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -212,7 +198,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x504006",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -224,7 +209,6 @@ 
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x500806",

        "PEBS": "1",

        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -236,7 +220,6 @@ 
        "EventName": "FRONTEND_RETIRED.STLB_MISS",

        "MSRIndex": "0x3F7",

        "MSRValue": "0x15",

        "PEBS": "1",

        "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"

tools/perf/pmu-events/arch/x86/tigerlake/memory.json

+2 −11
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "1009",

        "UMask": "0x1"
@@ -38,7 +37,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "20011",

        "UMask": "0x1"
@@ -51,7 +49,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "503",

        "UMask": "0x1"
@@ -64,7 +61,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "100007",

        "UMask": "0x1"
@@ -77,7 +73,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"
@@ -90,7 +85,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "101",

        "UMask": "0x1"
@@ -103,7 +97,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "2003",

        "UMask": "0x1"
@@ -116,7 +109,6 @@ 
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",

        "SampleAfterValue": "50021",

        "UMask": "0x1"
@@ -135,17 +127,16 @@ 
        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc9",

        "EventName": "RTM_RETIRED.ABORTED",

        "PEBS": "1",

        "PublicDescription": "Counts the number of times RTM abort was triggered.",

        "SampleAfterValue": "100003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",

        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc9",

        "EventName": "RTM_RETIRED.ABORTED_EVENTS",

        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",

        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).",

        "SampleAfterValue": "100003",

        "UMask": "0x80"

    },

tools/perf/pmu-events/arch/x86/tigerlake/metricgroups.json

+9 −1
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
    "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "LockCont": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",

    "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet",
@@ -83,7 +84,9 @@ 
    "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category",

    "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mispredicts category",

    "tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category",

    "tma_code_stlb_miss_group": "Metrics contributing to tma_code_stlb_miss category",

    "tma_core_bound_group": "Metrics contributing to tma_core_bound category",

    "tma_divider_group": "Metrics contributing to tma_divider category",

    "tma_dram_bound_group": "Metrics contributing to tma_dram_bound category",

    "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category",

    "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category",
@@ -93,6 +96,7 @@ 
    "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category",

    "tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category",

    "tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category",

    "tma_icache_misses_group": "Metrics contributing to tma_icache_misses category",

    "tma_issue2P": "Metrics related by the issue $issue2P",

    "tma_issueBM": "Metrics related by the issue $issueBM",

    "tma_issueBW": "Metrics related by the issue $issueBW",
@@ -112,10 +116,13 @@ 
    "tma_issueSpSt": "Metrics related by the issue $issueSpSt",

    "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn",

    "tma_issueTLB": "Metrics related by the issue $issueTLB",

    "tma_itlb_misses_group": "Metrics contributing to tma_itlb_misses category",

    "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category",

    "tma_l2_bound_group": "Metrics contributing to tma_l2_bound category",

    "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category",

    "tma_light_operations_group": "Metrics contributing to tma_light_operations category",

    "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category",

    "tma_load_stlb_miss_group": "Metrics contributing to tma_load_stlb_miss category",

    "tma_machine_clears_group": "Metrics contributing to tma_machine_clears category",

    "tma_mem_latency_group": "Metrics contributing to tma_mem_latency category",

    "tma_memory_bound_group": "Metrics contributing to tma_memory_bound category",
@@ -128,5 +135,6 @@ 
    "tma_retiring_group": "Metrics contributing to tma_retiring category",

    "tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category",

    "tma_store_bound_group": "Metrics contributing to tma_store_bound category",

    "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category"

    "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category",

    "tma_store_stlb_miss_group": "Metrics contributing to tma_store_stlb_miss category"

}