Commit 8db8f6ce authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Martin K. Petersen
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scsi: ufs: qcom: Add missing interconnect bandwidth values for Gear 5 



These entries are necessary to scale the interconnect bandwidth while
operating in Gear 5.

Cc: Amit Pundir <amit.pundir@linaro.org>
Fixes: 03ce80a1 ("scsi: ufs: qcom: Add support for scaling interconnects")
Tested-by: default avatarAmit Pundir <amit.pundir@linaro.org>
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240403-ufs-icc-fix-v2-1-958412a5eb45@linaro.org


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 4406e417

drivers/ufs/host/ufs-qcom.c

+7 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ enum { 
	TSTBUS_MAX,

};



#define QCOM_UFS_MAX_GEAR 4

#define QCOM_UFS_MAX_GEAR 5

#define QCOM_UFS_MAX_LANE 2



enum {
@@ -67,26 +67,32 @@ static const struct __ufs_qcom_bw_table { 
	[MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,		1000 },

	[MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,		1000 },

	[MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,		1000 },

	[MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752,		1000 },

	[MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,		1000 },

	[MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,		1000 },

	[MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,		1000 },

	[MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,		1000 },

	[MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504,		1000 },

	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,		1000 },

	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,		1000 },

	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },

	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },

	[MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800,	409600 },

	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,		1000 },

	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,		1000 },

	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },

	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },

	[MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800,	819200 },

	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,		1000 },

	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,		1000 },

	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },

	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },

	[MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800,	409600 },

	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,		1000 },

	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,		1000 },

	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },

	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },

	[MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800,	819200 },

	[MODE_MAX][0][0]		    = { 7643136,	307200 },

};