Unverified Commit 8df0cdcc authored by Alexandre Ghiti's avatar Alexandre Ghiti
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Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do &... 

Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency"

Conor Dooley <conor@kernel.org> says:

Since one depends on the other, albeit trivially, here's a v4 of the Zbb
toolchain dep removal alongside the rewording of Kconfig options I'd
sent out before the merge window. I think I like this implementation
better than v1, but I couldn't think of a good name for a "public"
version of __ALTERNATIVE(), so I used it here directly.
Unfortunately "ALTERNATIVE_2_CFG" already exists and I couldn't think of
a good way to name an alternative macro that allows for several config
options that didn't make the distinction sufficiently clear.. Yell
if you have better suggestions than I did.

I am a wee bit "worried" that this makes the Kconfig option confusing as
it isn't immediately obvious if someone is or is not going to get the
toolchain based optimisations.

Cheers,
Conor.

* patches from https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud:
  RISC-V: separate Zbb optimisations requiring and not requiring toolchain support
  RISC-V: clarify what some RISCV_ISA* config options do

Link: https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parents 4701f33a 9343aaba

arch/riscv/Kconfig

+20 −18
Original line number Diff line number Diff line
@@ -566,7 +566,8 @@ config RISCV_ISA_C 
	help

	  Adds "C" to the ISA subsets that the toolchain is allowed to emit

	  when building Linux, which results in compressed instructions in the

	  Linux binary.

	  Linux binary. This option produces a kernel that will not run on

	  systems that do not support compressed instructions.



	  If you don't know what to do here, say Y.
@@ -587,8 +588,8 @@ config RISCV_ISA_SVNAPOT 
	depends on RISCV_ALTERNATIVE

	default y

	help

	  Allow kernel to detect the Svnapot ISA-extension dynamically at boot

	  time and enable its usage.

	  Enable support for the Svnapot ISA-extension when it is detected

	  at boot.



	  The Svnapot extension is used to mark contiguous PTEs as a range

	  of contiguous virtual-to-physical translations for a naturally
@@ -606,9 +607,8 @@ config RISCV_ISA_SVPBMT 
	depends on RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the Svpbmt

	   ISA-extension (Supervisor-mode: page-based memory types) and

	   enable its usage.

	   Add support for the Svpbmt ISA-extension (Supervisor-mode:

	   page-based memory types) in the kernel when it is detected at boot.



	   The memory type for a page contains a combination of attributes

	   that indicate the cacheability, idempotency, and ordering
@@ -627,14 +627,15 @@ config TOOLCHAIN_HAS_V 
	depends on AS_HAS_OPTION_ARCH



config RISCV_ISA_V

	bool "VECTOR extension support"

	bool "Vector extension support"

	depends on TOOLCHAIN_HAS_V

	depends on FPU

	select DYNAMIC_SIGFRAME

	default y

	help

	  Say N here if you want to disable all vector related procedure

	  in the kernel.

	  Add support for the Vector extension when it is detected at boot.

	  When this option is disabled, neither the kernel nor userspace may

	  use vector procedures.



	  If you don't know what to do here, say Y.
@@ -747,12 +748,12 @@ config RISCV_ISA_ZBA 


config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZBB

	   extension (basic bit manipulation) and enable its usage.

	   Add support for enabling optimisations in the kernel when the

	   Zbb extension is detected at boot. Some optimisations may

	   additionally depend on toolchain support for Zbb.



	   The Zbb extension provides instructions to accelerate a number

	   of bit-specific operations (count bit population, sign extending,
@@ -791,9 +792,9 @@ config RISCV_ISA_ZICBOM 
	select RISCV_DMA_NONCOHERENT

	select DMA_DIRECT_REMAP

	help

	   Adds support to dynamically detect the presence of the ZICBOM

	   extension (Cache Block Management Operations) and enable its

	   usage.

	   Add support for the Zicbom extension (Cache Block Management

	   Operations) and enable its use in the kernel when it is detected

	   at boot.



	   The Zicbom extension can be used to handle for example

	   non-coherent DMA support on devices that need it.
@@ -806,7 +807,7 @@ config RISCV_ISA_ZICBOZ 
	default y

	help

	   Enable the use of the Zicboz extension (cbo.zero instruction)

	   when available.

	   in the kernel when it is detected at boot.



	   The Zicboz extension is used for faster zeroing of memory.
@@ -844,8 +845,9 @@ config FPU 
	bool "FPU support"

	default y

	help

	  Say N here if you want to disable all floating-point related procedure

	  in the kernel.

	  Add support for floating point operations when an FPU is detected at

	  boot. When this option is disabled, neither the kernel nor userspace

	  may use the floating point unit.



	  If you don't know what to do here, say Y.

arch/riscv/include/asm/arch_hweight.h

+3 −3
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


static __always_inline unsigned int __arch_hweight32(unsigned int w)

{

#ifdef CONFIG_RISCV_ISA_ZBB

#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)

	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,

				      RISCV_ISA_EXT_ZBB, 1)

			  : : : : legacy);
@@ -50,7 +50,7 @@ static inline unsigned int __arch_hweight8(unsigned int w) 
#if BITS_PER_LONG == 64

static __always_inline unsigned long __arch_hweight64(__u64 w)

{

# ifdef CONFIG_RISCV_ISA_ZBB

#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)

	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,

				      RISCV_ISA_EXT_ZBB, 1)

			  : : : : legacy);

arch/riscv/include/asm/bitops.h

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include <asm/barrier.h>

#include <asm/bitsperlong.h>



#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE)

#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE)

#include <asm-generic/bitops/__ffs.h>

#include <asm-generic/bitops/__fls.h>

#include <asm-generic/bitops/ffs.h>
@@ -175,7 +175,7 @@ static __always_inline int variable_fls(unsigned int x) 
	 variable_fls(x_);					\

})



#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */

#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */



#include <asm-generic/bitops/ffz.h>

#include <asm-generic/bitops/fls64.h>

arch/riscv/include/asm/checksum.h

+1 −2
Original line number Diff line number Diff line
@@ -49,8 +49,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) 
	 * ZBB only saves three instructions on 32-bit and five on 64-bit so not

	 * worth checking if supported without Alternatives.

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,

arch/riscv/lib/csum.c

+3 −18
Original line number Diff line number Diff line
@@ -40,12 +40,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, 
	uproto = (__force unsigned int)htonl(proto);

	sum += uproto;



	/*

	 * Zbb support saves 4 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*
@@ -157,12 +152,7 @@ do_csum_with_alignment(const unsigned char *buff, int len) 
	csum = do_csum_common(ptr, end, data);



#ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT

	/*

	 * Zbb support saves 6 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*
@@ -244,12 +234,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) 
	end = (const unsigned long *)(buff + len);

	csum = do_csum_common(ptr, end, data);



	/*

	 * Zbb support saves 6 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*