Commit 8efda8ae authored by Damien Le Moal's avatar Damien Le Moal Committed by Bjorn Helgaas
Browse files

PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding 

Move the code in rockchip_pcie_ep_probe() to hide the MSI-X capability
to its own function, rockchip_pcie_ep_hide_broken_msix_cap().

No functional changes.

Link: https://lore.kernel.org/r/20241017015849.190271-10-dlemoal@kernel.org


Signed-off-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 94564801

drivers/pci/controller/pcie-rockchip-ep.c

+30 −24
Original line number Diff line number Diff line
@@ -585,6 +585,34 @@ static void rockchip_pcie_ep_exit_ob_mem(struct rockchip_pcie_ep *ep) 
	pci_epc_mem_exit(ep->epc);

}



static void rockchip_pcie_ep_hide_broken_msix_cap(struct rockchip_pcie *rockchip)

{

	u32 cfg_msi, cfg_msix_cp;



	/*

	 * MSI-X is not supported but the controller still advertises the MSI-X

	 * capability by default, which can lead to the Root Complex side

	 * allocating MSI-X vectors which cannot be used. Avoid this by skipping

	 * the MSI-X capability entry in the PCIe capabilities linked-list: get

	 * the next pointer from the MSI-X entry and set that in the MSI

	 * capability entry (which is the previous entry). This way the MSI-X

	 * entry is skipped (left out of the linked-list) and not advertised.

	 */

	cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +

				     ROCKCHIP_PCIE_EP_MSI_CTRL_REG);



	cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;



	cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +

					 ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &

					 ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;



	cfg_msi |= cfg_msix_cp;



	rockchip_pcie_write(rockchip, cfg_msi,

			    PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);

}



static int rockchip_pcie_ep_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -592,7 +620,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) 
	struct rockchip_pcie *rockchip;

	struct pci_epc *epc;

	int err;

	u32 cfg_msi, cfg_msix_cp;



	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);

	if (!ep)
@@ -627,6 +654,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) 
	if (err)

		goto err_disable_clocks;



	rockchip_pcie_ep_hide_broken_msix_cap(rockchip);



	/* Establish the link automatically */

	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,

			    PCIE_CLIENT_CONFIG);
@@ -634,29 +663,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) 
	/* Only enable function 0 by default */

	rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);



	/*

	 * MSI-X is not supported but the controller still advertises the MSI-X

	 * capability by default, which can lead to the Root Complex side

	 * allocating MSI-X vectors which cannot be used. Avoid this by skipping

	 * the MSI-X capability entry in the PCIe capabilities linked-list: get

	 * the next pointer from the MSI-X entry and set that in the MSI

	 * capability entry (which is the previous entry). This way the MSI-X

	 * entry is skipped (left out of the linked-list) and not advertised.

	 */

	cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +

				     ROCKCHIP_PCIE_EP_MSI_CTRL_REG);



	cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;



	cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +

					 ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &

					 ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;



	cfg_msi |= cfg_msix_cp;



	rockchip_pcie_write(rockchip, cfg_msi,

			    PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);



	rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,

			    PCIE_CLIENT_CONFIG);