Commit 912d3c53 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774e1: Add cpuidle support for CA5x cores 



Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200827145315.26261-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ff9e786f

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ a57_0: cpu@0 { 
			power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			dynamic-power-coefficient = <854>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;
@@ -141,6 +142,7 @@ a57_1: cpu@1 { 
			power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -154,6 +156,7 @@ a57_2: cpu@2 { 
			power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -167,6 +170,7 @@ a57_3: cpu@3 { 
			power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

			capacity-dmips-mhz = <1024>;
@@ -180,6 +184,7 @@ a53_0: cpu@100 { 
			power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_1>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <277>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
@@ -194,6 +199,7 @@ a53_1: cpu@101 { 
			power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_1>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

			capacity-dmips-mhz = <535>;
@@ -206,6 +212,7 @@ a53_2: cpu@102 { 
			power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_1>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

			capacity-dmips-mhz = <535>;
@@ -218,6 +225,7 @@ a53_3: cpu@103 { 
			power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_1>;

			clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

			capacity-dmips-mhz = <535>;
@@ -236,6 +244,28 @@ L2_CA53: cache-controller-1 { 
			cache-unified;

			cache-level = <2>;

		};



		idle-states {

			entry-method = "psci";



			CPU_SLEEP_0: cpu-sleep-0 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010000>;

				local-timer-stop;

				entry-latency-us = <400>;

				exit-latency-us = <500>;

				min-residency-us = <4000>;

			};



			CPU_SLEEP_1: cpu-sleep-1 {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010000>;

				local-timer-stop;

				entry-latency-us = <700>;

				exit-latency-us = <700>;

				min-residency-us = <5000>;

			};

		};

	};



	extal_clk: extal {