Unverified Commit 917c8d19 authored by Lucas Stach's avatar Lucas Stach Committed by Robert Foss
Browse files

drm/bridge: analogix_dp: don't wait for PLL lock too early 



The PLL will be reconfigured later, which may cause it to go out of lock
anyway, so there is no point in waiting for the PLL to lock here. Instead
we can continue execution of the link setup, which will properly set the
PLL parameters and will wait for the PLL to lock at the appropriate times.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarRobert Foss <rfoss@kernel.org>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619182200.3752465-11-l.stach@pengutronix.de
parent 90986e35

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

+1 −13
Original line number Diff line number Diff line
@@ -356,7 +356,6 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 
int analogix_dp_init_analog_func(struct analogix_dp_device *dp)

{

	u32 reg;

	int timeout_loop = 0;



	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
@@ -368,19 +367,8 @@ int analogix_dp_init_analog_func(struct analogix_dp_device *dp) 
	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);



	/* Power up PLL */

	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {

	analogix_dp_set_pll_power_down(dp, 0);



		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {

			timeout_loop++;

			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {

				dev_err(dp->dev, "failed to get pll lock status\n");

				return -ETIMEDOUT;

			}

			usleep_range(10, 20);

		}

	}



	/* Enable Serdes FIFO function and Link symbol clock domain module */

	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);

	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N