Commit 91f815b7 authored by Chao-ying Fu's avatar Chao-ying Fu Committed by Paul Walmsley
Browse files

riscv: Update MIPS vendor id to 0x127 

[1] defines MIPS vendor id as 0x127. All previous MIPS RISC-V patches
were tested on QEMU, also modified to use 0x722 as MIPS_VENDOR_ID. This
new value should reflect real hardware.

[1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf



Fixes: a8fed1bc ("riscv: Add xmipsexectl as a vendor extension")
Signed-off-by: default avatarChao-ying Fu <cfu@wavecomp.com>
Signed-off-by: default avatarAleksa Paunovic <aleksa.paunovic@htecgroup.com>
Link: https://patch.msgid.link/20251113-mips-vendorid-v2-1-3279489b7f84@htecgroup.com


Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarPaul WAlmsley <pjw@kernel.org>
parent 4427259c

arch/riscv/include/asm/vendorid_list.h

+1 −1
Original line number Diff line number Diff line
@@ -7,8 +7,8 @@ 


#define ANDES_VENDOR_ID		0x31e

#define MICROCHIP_VENDOR_ID	0x029

#define MIPS_VENDOR_ID		0x127

#define SIFIVE_VENDOR_ID	0x489

#define THEAD_VENDOR_ID		0x5b7

#define MIPS_VENDOR_ID		0x722



#endif