Unverified Commit 94079362 authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
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drm/xe: Mark ROW_CHICKEN5 as a masked register 



ROW_CHICKEN5 is a masked register (i.e., to adjust the value of any of
the lower 16 bits, the corresponding bit in the upper 16 bits must also
be set).  Add the XE_REG_OPTION_MASKED to its definition; failure to do
so will cause workaround updates of this register to not apply properly.

Bspec: 56853
Fixes: 835cd6cb ("drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10")
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260410-xe3p_tuning-v1-3-e206a62ee38f@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
(cherry picked from commit cd84bfbba7feb4c1e72356f14de026dfda1a9e2a)
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 2299d735

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -583,7 +583,7 @@ 
#define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)

#define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)



#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)

#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED)

#define   CPSS_AWARE_DIS			REG_BIT(3)



#define SARB_CHICKEN1				XE_REG_MCR(0xe90c)