Commit 94467a22 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.14-tag2' of... 

Merge tag 'renesas-pinctrl-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

pinctrl: renesas: Updates for v6.14 (take two)

  - Add support for alpha-numerical port references on the RZ/V2H SoC,
  - Add support for the RZ/G3E (R9A09G047) Soc.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents cef4f1b5 829356da

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+9 −6
Original line number Diff line number Diff line
@@ -4,19 +4,22 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

    maxItems: 1
@@ -37,7 +40,7 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+5 −2
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ properties: 
              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

              - renesas,r9a08g045-pinctrl # RZ/G3S

              - renesas,r9a09g047-pinctrl # RZ/G3E

              - renesas,r9a09g057-pinctrl # RZ/V2H(P)



      - items:
@@ -125,7 +126,7 @@ additionalProperties: 
        drive-push-pull: true

        renesas,output-impedance:

          description:

            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this

            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this

            property corresponds to register bit values that can be set in the PFC_IOLH_mn

            register, which adjusts the drive strength value and is pin-dependent.

          $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf: 
      properties:

        compatible:

          contains:

            const: renesas,r9a09g057-pinctrl

            enum:

              - renesas,r9a09g047-pinctrl

              - renesas,r9a09g057-pinctrl

    then:

      properties:

        resets:

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

+17 −0
Original line number Diff line number Diff line
@@ -525,6 +525,23 @@ properties: 
              - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0

          - const: renesas,r9a09g011



      - description: RZ/G3E (R9A09G047)

        items:

          - enum:

              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK

          - enum:

              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)

          - enum:

              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

drivers/pinctrl/renesas/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ config PINCTRL_RENESAS 
	select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0

	select PINCTRL_RZG2L if ARCH_RZG2L

	select PINCTRL_RZV2M if ARCH_R9A09G011

	select PINCTRL_RZG2L if ARCH_R9A09G047

	select PINCTRL_RZG2L if ARCH_R9A09G057

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+180 −6
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ 
#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>



#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>

#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>

#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>



#include "../core.h"
@@ -381,13 +383,51 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 
	return 0;

}



static const u64 r9a09g047_variable_pin_cfg[] = {

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),

};



static const u64 r9a09g057_variable_pin_cfg[] = {

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

};



#ifdef CONFIG_RISCV
@@ -1962,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)),			/* P18 */

};



static const char * const rzg3e_gpio_names[] = {

	"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",

	"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",

	"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",

	"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",

	"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",

	"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",

	"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",

	"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",

	"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",

	"",    "",    "",    "",    "",    "",    "",    "",

	"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",

	"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",

	"PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",

	"PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",

	"PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",

	"PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",

	"PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",

	"PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",

	"",    "",    "",    "",    "",    "",    "",    "",

	"PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",

	"PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",

	"PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",

	"PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",

	"",    "",    "",    "",    "",    "",    "",    "",

	"",    "",    "",    "",    "",    "",    "",    "",

	"",    "",    "",    "",    "",    "",    "",    "",

	"",    "",    "",    "",    "",    "",    "",    "",

	"",    "",    "",    "",    "",    "",    "",    "",

	"PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",

};



static const u64 r9a09g047_gpio_configs[] = {

	RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS),	/* P0 */

	RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |

				      PIN_CFG_ELC),		/* P1 */

	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |

				      PIN_CFG_NOD),		/* P2 */

	RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS),	/* P3 */

	RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS),	/* P4 */

	RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS),	/* P5 */

	RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS),	/* P6 */

	RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |

				      PIN_CFG_ELC),		/* P7 */

	RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS),	/* P8 */

	0x0,

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a),			/* PA */

	RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS),	/* PB */

	RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS),	/* PC */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d),			/* PD */

	RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS),	/* PE */

	RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS),	/* PF */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30),			/* PG */

	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31),			/* PH */

	0x0,

	RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33),			/* PJ */

	RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS),	/* PK */

	RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS),	/* PL */

	RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS),	/* PM */

	0x0,

	0x0,

	0x0,

	0x0,

	0x0,

	RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS),	/* PS */

};



static const char * const rzv2h_gpio_names[] = {

	"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",

	"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
@@ -2252,6 +2359,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { 
	{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },

};



static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {

	{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },

	{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },

	{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },

	{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },

	{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },

	{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },

	{ "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },

	{ "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },

	{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

	{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,

	 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },

};



static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)

{

	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
@@ -2762,6 +2906,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) 
	BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >

		     ARRAY_SIZE(rzg2l_gpio_names));



	BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >

		     ARRAY_SIZE(rzg3e_gpio_names));



	BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >

		     ARRAY_SIZE(rzv2h_gpio_names));
@@ -3160,6 +3307,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { 
	.bias_param_to_hw = &rzg2l_bias_param_to_hw,

};



static struct rzg2l_pinctrl_data r9a09g047_data = {

	.port_pins = rzg3e_gpio_names,

	.port_pin_configs = r9a09g047_gpio_configs,

	.n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),

	.dedicated_pins = rzg3e_dedicated_pins,

	.n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,

	.n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),

	.hwcfg = &rzv2h_hwcfg,

	.variable_pin_cfg = r9a09g047_variable_pin_cfg,

	.n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),

	.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),

	.custom_params = renesas_rzv2h_custom_bindings,

#ifdef CONFIG_DEBUG_FS

	.custom_conf_items = renesas_rzv2h_conf_items,

#endif

	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzv2h_pmc_writeb,

	.oen_read = &rzv2h_oen_read,

	.oen_write = &rzv2h_oen_write,

	.hw_to_bias_param = &rzv2h_hw_to_bias_param,

	.bias_param_to_hw = &rzv2h_bias_param_to_hw,

};



static struct rzg2l_pinctrl_data r9a09g057_data = {

	.port_pins = rzv2h_gpio_names,

	.port_pin_configs = r9a09g057_gpio_configs,
@@ -3196,6 +3366,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { 
		.compatible = "renesas,r9a08g045-pinctrl",

		.data = &r9a08g045_data,

	},

	{

		.compatible = "renesas,r9a09g047-pinctrl",

		.data = &r9a09g047_data,

	},

	{

		.compatible = "renesas,r9a09g057-pinctrl",

		.data = &r9a09g057_data,