Unverified Commit 94debe5e authored by Venkata Prasad Potturu's avatar Venkata Prasad Potturu Committed by Mark Brown
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ASoC: SOF: amd: Fix for incorrect DMA ch status register offset 



DMA ch status register offset change in acp7.0 platform

Incorrect DMA channel status register offset check lead to
firmware boot failure.

[   14.432497] snd_sof_amd_acp70 0000:c4:00.5: ------------[ DSP dump start ]------------
[   14.432533] snd_sof_amd_acp70 0000:c4:00.5: Firmware boot failure due to timeout
[   14.432549] snd_sof_amd_acp70 0000:c4:00.5: fw_state: SOF_FW_BOOT_IN_PROGRESS (3)
[   14.432610] snd_sof_amd_acp70 0000:c4:00.5: invalid header size 0x71c41000. FW oops is bogus
[   14.432626] snd_sof_amd_acp70 0000:c4:00.5: unexpected fault 0x71c40000 trace 0x71c40000
[   14.432642] snd_sof_amd_acp70 0000:c4:00.5: ------------[ DSP dump end ]------------
[   14.432657] snd_sof_amd_acp70 0000:c4:00.5: error: failed to boot DSP firmware -5
[   14.432672] snd_sof_amd_acp70 0000:c4:00.5: fw_state change: 3 -> 4
[   14.433260] dmic-codec dmic-codec: ASoC: Unregistered DAI 'dmic-hifi'
[   14.433319] snd_sof_amd_acp70 0000:c4:00.5: fw_state change: 4 -> 0
[   14.433358] snd_sof_amd_acp70 0000:c4:00.5: error: sof_probe_work failed err: -5

Update correct register offset for DMA ch status register.

Fixes: 490be7ba ("ASoC: SOF: amd: add support for acp7.0 based platform")

Signed-off-by: default avatarVenkata Prasad Potturu <venkataprasad.potturu@amd.com>
Link: https://patch.msgid.link/20241106142658.1240929-1-venkataprasad.potturu@amd.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent de156f3c

sound/soc/sof/amd/acp.c

+9 −1
Original line number Diff line number Diff line
@@ -342,11 +342,19 @@ int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 
{

	struct snd_sof_dev *sdev = adata->dev;

	unsigned int val;

	unsigned int acp_dma_ch_sts;

	int ret = 0;



	switch (adata->pci_rev) {

	case ACP70_PCI_ID:

		acp_dma_ch_sts = ACP70_DMA_CH_STS;

		break;

	default:

		acp_dma_ch_sts = ACP_DMA_CH_STS;

	}

	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));

	if (val & ACP_DMA_CH_RUN) {

		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val,

		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val,

						    ACP_REG_POLL_INTERVAL,

						    ACP_DMA_COMPLETE_TIMEOUT_US);

		if (ret < 0)