Commit 967a94a9 authored by Chen Wang's avatar Chen Wang Committed by Conor Dooley
Browse files

riscv: dts: add initial Sophgo SG2042 SoC device tree 

Milk-V Pioneer motherboard is powered by SG2042.

SG2042 is server grade chip with high performance, low power
consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores
- 4 cores per cluster, 16 clusters on chip
- More info is available at [1].

Currently only support booting into console with only uart,
other features will be added soon later.

Link: https://en.sophgo.com/product/introduce/sg2042.html

 [1]
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Acked-by: default avatarChao Wei <chao.wei@sophgo.com>
Co-developed-by: default avatarXiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: default avatarXiaoguang Xing <xiaoguang.xing@sophgo.com>
Co-developed-by: default avatarInochi Amaoto <inochiama@outlook.com>
Signed-off-by: default avatarInochi Amaoto <inochiama@outlook.com>
Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 942e02e1

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES 
M:	Chao Wei <chao.wei@sophgo.com>

M:	Chen Wang <unicorn_wang@outlook.com>

S:	Maintained

F:	arch/riscv/boot/dts/sophgo/

F:	Documentation/devicetree/bindings/riscv/sophgo.yaml









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arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
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arch/riscv/boot/dts/sophgo/sg2042.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)









/*









 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.









 */



















/dts-v1/;









#include <dt-bindings/interrupt-controller/irq.h>



















#include "sg2042-cpus.dtsi"



















/ {









	compatible = "sophgo,sg2042";









	#address-cells = <2>;









	#size-cells = <2>;









	dma-noncoherent;



















	aliases {









		serial0 = &uart0;









	};



















	soc: soc {









		compatible = "simple-bus";









		#address-cells = <2>;









		#size-cells = <2>;









		ranges;



















		clint_mswi: interrupt-controller@7094000000 {









			compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";









			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;









			interrupts-extended = <&cpu0_intc 3>,









					      <&cpu1_intc 3>,









					      <&cpu2_intc 3>,









					      <&cpu3_intc 3>,









					      <&cpu4_intc 3>,









					      <&cpu5_intc 3>,









					      <&cpu6_intc 3>,









					      <&cpu7_intc 3>,









					      <&cpu8_intc 3>,









					      <&cpu9_intc 3>,









					      <&cpu10_intc 3>,









					      <&cpu11_intc 3>,









					      <&cpu12_intc 3>,









					      <&cpu13_intc 3>,









					      <&cpu14_intc 3>,









					      <&cpu15_intc 3>,









					      <&cpu16_intc 3>,









					      <&cpu17_intc 3>,









					      <&cpu18_intc 3>,









					      <&cpu19_intc 3>,









					      <&cpu20_intc 3>,









					      <&cpu21_intc 3>,









					      <&cpu22_intc 3>,









					      <&cpu23_intc 3>,









					      <&cpu24_intc 3>,









					      <&cpu25_intc 3>,









					      <&cpu26_intc 3>,









					      <&cpu27_intc 3>,









					      <&cpu28_intc 3>,









					      <&cpu29_intc 3>,









					      <&cpu30_intc 3>,









					      <&cpu31_intc 3>,









					      <&cpu32_intc 3>,









					      <&cpu33_intc 3>,









					      <&cpu34_intc 3>,









					      <&cpu35_intc 3>,









					      <&cpu36_intc 3>,









					      <&cpu37_intc 3>,









					      <&cpu38_intc 3>,









					      <&cpu39_intc 3>,









					      <&cpu40_intc 3>,









					      <&cpu41_intc 3>,









					      <&cpu42_intc 3>,









					      <&cpu43_intc 3>,









					      <&cpu44_intc 3>,









					      <&cpu45_intc 3>,









					      <&cpu46_intc 3>,









					      <&cpu47_intc 3>,









					      <&cpu48_intc 3>,









					      <&cpu49_intc 3>,









					      <&cpu50_intc 3>,









					      <&cpu51_intc 3>,









					      <&cpu52_intc 3>,









					      <&cpu53_intc 3>,









					      <&cpu54_intc 3>,









					      <&cpu55_intc 3>,









					      <&cpu56_intc 3>,









					      <&cpu57_intc 3>,









					      <&cpu58_intc 3>,









					      <&cpu59_intc 3>,









					      <&cpu60_intc 3>,









					      <&cpu61_intc 3>,









					      <&cpu62_intc 3>,









					      <&cpu63_intc 3>;









		};



















		clint_mtimer0: timer@70ac000000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu0_intc 7>,









					      <&cpu1_intc 7>,









					      <&cpu2_intc 7>,









					      <&cpu3_intc 7>;









		};



















		clint_mtimer1: timer@70ac010000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu4_intc 7>,









					      <&cpu5_intc 7>,









					      <&cpu6_intc 7>,









					      <&cpu7_intc 7>;









		};



















		clint_mtimer2: timer@70ac020000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu8_intc 7>,









					      <&cpu9_intc 7>,









					      <&cpu10_intc 7>,









					      <&cpu11_intc 7>;









		};



















		clint_mtimer3: timer@70ac030000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu12_intc 7>,









					      <&cpu13_intc 7>,









					      <&cpu14_intc 7>,









					      <&cpu15_intc 7>;









		};



















		clint_mtimer4: timer@70ac040000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu16_intc 7>,









					      <&cpu17_intc 7>,









					      <&cpu18_intc 7>,









					      <&cpu19_intc 7>;









		};



















		clint_mtimer5: timer@70ac050000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu20_intc 7>,









					      <&cpu21_intc 7>,









					      <&cpu22_intc 7>,









					      <&cpu23_intc 7>;









		};



















		clint_mtimer6: timer@70ac060000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu24_intc 7>,









					      <&cpu25_intc 7>,









					      <&cpu26_intc 7>,









					      <&cpu27_intc 7>;









		};



















		clint_mtimer7: timer@70ac070000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu28_intc 7>,









					      <&cpu29_intc 7>,









					      <&cpu30_intc 7>,









					      <&cpu31_intc 7>;









		};



















		clint_mtimer8: timer@70ac080000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu32_intc 7>,









					      <&cpu33_intc 7>,









					      <&cpu34_intc 7>,









					      <&cpu35_intc 7>;









		};



















		clint_mtimer9: timer@70ac090000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu36_intc 7>,









					      <&cpu37_intc 7>,









					      <&cpu38_intc 7>,









					      <&cpu39_intc 7>;









		};



















		clint_mtimer10: timer@70ac0a0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu40_intc 7>,









					      <&cpu41_intc 7>,









					      <&cpu42_intc 7>,









					      <&cpu43_intc 7>;









		};



















		clint_mtimer11: timer@70ac0b0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu44_intc 7>,









					      <&cpu45_intc 7>,









					      <&cpu46_intc 7>,









					      <&cpu47_intc 7>;









		};



















		clint_mtimer12: timer@70ac0c0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu48_intc 7>,









					      <&cpu49_intc 7>,









					      <&cpu50_intc 7>,









					      <&cpu51_intc 7>;









		};



















		clint_mtimer13: timer@70ac0d0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu52_intc 7>,









					      <&cpu53_intc 7>,









					      <&cpu54_intc 7>,









					      <&cpu55_intc 7>;









		};



















		clint_mtimer14: timer@70ac0e0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu56_intc 7>,









					      <&cpu57_intc 7>,









					      <&cpu58_intc 7>,









					      <&cpu59_intc 7>;









		};



















		clint_mtimer15: timer@70ac0f0000 {









			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";









			reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;









			interrupts-extended = <&cpu60_intc 7>,









					      <&cpu61_intc 7>,









					      <&cpu62_intc 7>,









					      <&cpu63_intc 7>;









		};



















		intc: interrupt-controller@7090000000 {









			compatible = "sophgo,sg2042-plic", "thead,c900-plic";









			#address-cells = <0>;









			#interrupt-cells = <2>;









			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;









			interrupt-controller;









			interrupts-extended =









				<&cpu0_intc 11>,  <&cpu0_intc 9>,









				<&cpu1_intc 11>,  <&cpu1_intc 9>,









				<&cpu2_intc 11>,  <&cpu2_intc 9>,









				<&cpu3_intc 11>,  <&cpu3_intc 9>,









				<&cpu4_intc 11>,  <&cpu4_intc 9>,









				<&cpu5_intc 11>,  <&cpu5_intc 9>,









				<&cpu6_intc 11>,  <&cpu6_intc 9>,









				<&cpu7_intc 11>,  <&cpu7_intc 9>,









				<&cpu8_intc 11>,  <&cpu8_intc 9>,









				<&cpu9_intc 11>,  <&cpu9_intc 9>,









				<&cpu10_intc 11>, <&cpu10_intc 9>,









				<&cpu11_intc 11>, <&cpu11_intc 9>,









				<&cpu12_intc 11>, <&cpu12_intc 9>,









				<&cpu13_intc 11>, <&cpu13_intc 9>,









				<&cpu14_intc 11>, <&cpu14_intc 9>,









				<&cpu15_intc 11>, <&cpu15_intc 9>,









				<&cpu16_intc 11>, <&cpu16_intc 9>,









				<&cpu17_intc 11>, <&cpu17_intc 9>,









				<&cpu18_intc 11>, <&cpu18_intc 9>,









				<&cpu19_intc 11>, <&cpu19_intc 9>,









				<&cpu20_intc 11>, <&cpu20_intc 9>,









				<&cpu21_intc 11>, <&cpu21_intc 9>,









				<&cpu22_intc 11>, <&cpu22_intc 9>,









				<&cpu23_intc 11>, <&cpu23_intc 9>,









				<&cpu24_intc 11>, <&cpu24_intc 9>,









				<&cpu25_intc 11>, <&cpu25_intc 9>,









				<&cpu26_intc 11>, <&cpu26_intc 9>,









				<&cpu27_intc 11>, <&cpu27_intc 9>,









				<&cpu28_intc 11>, <&cpu28_intc 9>,









				<&cpu29_intc 11>, <&cpu29_intc 9>,









				<&cpu30_intc 11>, <&cpu30_intc 9>,









				<&cpu31_intc 11>, <&cpu31_intc 9>,









				<&cpu32_intc 11>, <&cpu32_intc 9>,









				<&cpu33_intc 11>, <&cpu33_intc 9>,









				<&cpu34_intc 11>, <&cpu34_intc 9>,









				<&cpu35_intc 11>, <&cpu35_intc 9>,









				<&cpu36_intc 11>, <&cpu36_intc 9>,









				<&cpu37_intc 11>, <&cpu37_intc 9>,









				<&cpu38_intc 11>, <&cpu38_intc 9>,









				<&cpu39_intc 11>, <&cpu39_intc 9>,









				<&cpu40_intc 11>, <&cpu40_intc 9>,









				<&cpu41_intc 11>, <&cpu41_intc 9>,









				<&cpu42_intc 11>, <&cpu42_intc 9>,









				<&cpu43_intc 11>, <&cpu43_intc 9>,









				<&cpu44_intc 11>, <&cpu44_intc 9>,









				<&cpu45_intc 11>, <&cpu45_intc 9>,









				<&cpu46_intc 11>, <&cpu46_intc 9>,









				<&cpu47_intc 11>, <&cpu47_intc 9>,









				<&cpu48_intc 11>, <&cpu48_intc 9>,









				<&cpu49_intc 11>, <&cpu49_intc 9>,









				<&cpu50_intc 11>, <&cpu50_intc 9>,









				<&cpu51_intc 11>, <&cpu51_intc 9>,









				<&cpu52_intc 11>, <&cpu52_intc 9>,









				<&cpu53_intc 11>, <&cpu53_intc 9>,









				<&cpu54_intc 11>, <&cpu54_intc 9>,









				<&cpu55_intc 11>, <&cpu55_intc 9>,









				<&cpu56_intc 11>, <&cpu56_intc 9>,









				<&cpu57_intc 11>, <&cpu57_intc 9>,









				<&cpu58_intc 11>, <&cpu58_intc 9>,









				<&cpu59_intc 11>, <&cpu59_intc 9>,









				<&cpu60_intc 11>, <&cpu60_intc 9>,









				<&cpu61_intc 11>, <&cpu61_intc 9>,









				<&cpu62_intc 11>, <&cpu62_intc 9>,









				<&cpu63_intc 11>, <&cpu63_intc 9>;









			riscv,ndev = <224>;









		};



















		uart0: serial@7040000000 {









			compatible = "snps,dw-apb-uart";









			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;









			interrupt-parent = <&intc>;









			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;









			clock-frequency = <500000000>;









			reg-shift = <2>;









			reg-io-width = <4>;









			status = "disabled";









		};









	};









};