Commit 988699f9 authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Marc Zyngier
Browse files

arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability 



Implement the GCIE capability as a strict boot cpu capability to
detect whether architectural GICv5 support is available in HW.

Plug it in with a naming consistent with the existing GICv3
CPU interface capability.

Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-17-12e71f1b3528@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 0bb5b6fa

arch/arm64/kernel/cpufeature.c

+7 −0
Original line number Diff line number Diff line
@@ -3061,6 +3061,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_pmuv3,

	},

#endif

	{

		.desc = "GICv5 CPU interface",

		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,

		.capability = ARM64_HAS_GICV5_CPUIF,

		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP)

	},

	{},

};

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 
HAS_GENERIC_AUTH_ARCH_QARMA5

HAS_GENERIC_AUTH_IMP_DEF

HAS_GICV3_CPUIF

HAS_GICV5_CPUIF

HAS_GIC_PRIO_MASKING

HAS_GIC_PRIO_RELAXED_SYNC

HAS_HCR_NV1