Commit 988c9e70 authored by Somalapuram Amaranath's avatar Somalapuram Amaranath Committed by Alex Deucher
Browse files

drm/amdgpu: enable userqueue support for GFX12



This patch enables Usermode queue support across GFX, Compute
and SDMA IPs on GFX12/SDMA7. It typically reuses Navi3X userqueue
IP functions to create and destroy MQDs.

v2: rebase on proposed changes (Alex)

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Cc: Arvind Yadav <arvind.yadav@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSomalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 79819d9a
Loading
Loading
Loading
Loading
+5 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@
#include "gfx_v12_0.h"
#include "nbif_v6_3_1.h"
#include "mes_v12_0.h"
#include "mes_userqueue.h"

#define GFX12_NUM_GFX_RINGS	1
#define GFX12_MEC_HPD_SIZE	2048
@@ -1417,6 +1418,10 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
		adev->gfx.mec.num_mec = 1;
		adev->gfx.mec.num_pipe_per_mec = 2;
		adev->gfx.mec.num_queue_per_pipe = 4;
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
#endif
		break;
	default:
		adev->gfx.me.num_me = 1;
+6 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@
#include "sdma_common.h"
#include "sdma_v7_0.h"
#include "v12_structs.h"
#include "mes_userqueue.h"

MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin");
MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin");
@@ -1381,6 +1382,11 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
	else
		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");

#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
	adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
#endif


	return r;
}