Commit 9b454a34 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2026-04-02' of... 

Merge tag 'drm-intel-fixes-2026-04-02' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-fixes

- Fix for #12045: Huawei Matebook E (DRR-WXX): Persistent Black Screen on Boot with i915 and Gen11: Modesetting and Backlight Control Malfunction
- Fix for #15826: i915: Raptor Lake-P [UHD Graphics] display flicker/corruption on eDP panel
- Use crtc_state->enhanced_framing properly on ivb/hsw CPU eDP

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patch.msgid.link/ac5DM1IpBkuaT58e@jlahtine-mobl
parents 2aa5a6d9 9c9a57e4

drivers/gpu/drm/i915/display/g4x_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
			intel_dp->DP |= DP_SYNC_VS_HIGH;

		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;



		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

		if (pipe_config->enhanced_framing)

			intel_dp->DP |= DP_ENHANCED_FRAMING;



		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -889,7 +889,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	 * non-compressed link speeds, and simplifies down to the ratio between

	 * compressed and non-compressed bpp.

	 */

	if (crtc_state->dsc.compression_enable) {

	if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {

		mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);

		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	}
@@ -1503,7 +1503,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, 
	struct drm_display_mode *adjusted_mode =

					&pipe_config->hw.adjusted_mode;



	if (pipe_config->dsc.compressed_bpp_x16) {

	if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {

		int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);

		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

drivers/gpu/drm/i915/display/intel_cdclk.c

+54 −0
Original line number Diff line number Diff line
@@ -2971,6 +2971,53 @@ static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 
	return 0;

}



static int intel_cdclk_update_crtc_min_voltage_level(struct intel_atomic_state *state,

						     struct intel_crtc *crtc,

						     u8 old_min_voltage_level,

						     u8 new_min_voltage_level,

						     bool *need_cdclk_calc)

{

	struct intel_display *display = to_intel_display(state);

	struct intel_cdclk_state *cdclk_state;

	bool allow_voltage_level_decrease = intel_any_crtc_needs_modeset(state);

	int ret;



	if (new_min_voltage_level == old_min_voltage_level)

		return 0;



	if (!allow_voltage_level_decrease &&

	    new_min_voltage_level < old_min_voltage_level)

		return 0;



	cdclk_state = intel_atomic_get_cdclk_state(state);

	if (IS_ERR(cdclk_state))

		return PTR_ERR(cdclk_state);



	old_min_voltage_level = cdclk_state->min_voltage_level[crtc->pipe];



	if (new_min_voltage_level == old_min_voltage_level)

		return 0;



	if (!allow_voltage_level_decrease &&

	    new_min_voltage_level < old_min_voltage_level)

		return 0;



	cdclk_state->min_voltage_level[crtc->pipe] = new_min_voltage_level;



	ret = intel_atomic_lock_global_state(&cdclk_state->base);

	if (ret)

		return ret;



	*need_cdclk_calc = true;



	drm_dbg_kms(display->drm,

		    "[CRTC:%d:%s] min voltage level: %d -> %d\n",

		    crtc->base.base.id, crtc->base.name,

		    old_min_voltage_level, new_min_voltage_level);



	return 0;

}



int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,

					 int old_min_cdclk, int new_min_cdclk,

					 bool *need_cdclk_calc)
@@ -3386,6 +3433,13 @@ static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 
							need_cdclk_calc);

		if (ret)

			return ret;



		ret = intel_cdclk_update_crtc_min_voltage_level(state, crtc,

								old_crtc_state->min_voltage_level,

								new_crtc_state->min_voltage_level,

								need_cdclk_calc);

		if (ret)

			return ret;

	}



	return 0;