Commit 9b71be87 authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Add core reset registers for JPEG5_0_1 



Add core reset control register definitions and align
all prior register definitions to end at 100 column
length for uniformity.

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent da120ed5

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h

+68 −60
Original line number Diff line number Diff line
@@ -86,5 +86,13 @@ extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block; 
#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX                                                 1

#define regUVD_JRBC9_UVD_JRBC_RB_RPTR                                                         0x044a

#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX                                                1

#define regUVD_JMI0_JPEG_LMI_DROP                                                             0x0663

#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX                                                    1

#define regUVD_JMI0_UVD_JMI_CLIENT_STALL                                                      0x067a

#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX                                             1

#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS                                               0x067b

#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX                                      1

#define regJPEG_CORE_RST_CTRL                                                                 0x072e

#define regJPEG_CORE_RST_CTRL_BASE_IDX                                                        1



#endif /* __JPEG_V5_0_0_H__ */