Commit 9e5d4a5e authored Sep 09, 2025 by Alvin Lee Committed by Alex Deucher Sep 23, 2025

drm/amd/display: Use mpc.preblend flag to indicate preblend



[Description]
Modifications in per asic capability means mpc.preblend flag should be used
to indicate preblend. Update relevant paths to use this flag.

Fixes: 39923050 ("drm/amd/display: Clear DPP 3DLUT Cap")
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 0bf6b216

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -821,7 +821,7 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
		struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
		const struct drm_color_lut shaper = NULL, lut3d = NULL;
		uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE;
		bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut;
		bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut \|\| adev->dm.dc->caps.color.mpc.preblend;

		/* shaper LUT is only available if 3D LUT color caps */
		exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1633,7 +1633,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
		drm_object_attach_property(&plane->base,
		dm->adev->mode_info.plane_ctm_property, 0);

		if (dpp_color_caps.hw_3d_lut) {
		if (dpp_color_caps.hw_3d_lut \|\| dm->dc->caps.color.mpc.preblend) {
		drm_object_attach_property(&plane->base,
		mode_info.plane_shaper_lut_property, 0);
		drm_object_attach_property(&plane->base,