Commit 9f393d8e authored by Sergey Matyukevich's avatar Sergey Matyukevich Committed by Chen-Yu Tsai
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riscv: dts: allwinner: d1: fix vlenb property 

According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.

[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf



Fixes: ce1daeeb ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: default avatarSergey Matyukevich <geomatsi@gmail.com>
Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com


Signed-off-by: default avatarChen-Yu Tsai <wens@kernel.org>
parent 3a866087

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ cpu0: cpu@0 { 
			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",

					       "zifencei", "zihpm", "xtheadvector";

			thead,vlenb = <128>;

			thead,vlenb = <16>;

			#cooling-cells = <2>;



			cpu0_intc: interrupt-controller {